Self-Shut-Off Pulsed Latches for Minimizing Sequencing Overhead
In this study, a self-shut-off pulsed latch (SSPL) is proposed as sequencing elements for reducing the hold time constraint. As SSPL captures the data input after the clock edge, the large setup-time problem that exists in the master-slave flip-flop (MSFF) is eliminated. In addition, the transparenc...
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| Veröffentlicht in: | IEEE transactions on very large scale integration (VLSI) systems 2022-11, Vol.30 (11), p.1728-1738 |
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| container_title | IEEE transactions on very large scale integration (VLSI) systems |
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| creator | Park, Hyunho Jeong, Hanwool |
| description | In this study, a self-shut-off pulsed latch (SSPL) is proposed as sequencing elements for reducing the hold time constraint. As SSPL captures the data input after the clock edge, the large setup-time problem that exists in the master-slave flip-flop (MSFF) is eliminated. In addition, the transparency windows are closed immediately after successfully capturing the data input (self-shut-off), and the proposed SSPL is devoid of the large hold-time problem existing in conventional pulsed latches. According to the 7-nm FinFET postlayout simulation results, the sequencing timing overheads improved by 40% and 36% in SSPL, in comparison with the conventional MSFF at V_{\mathrm {DD}} =0.4 and 1.0 V, respectively. Furthermore, the hold time reduced by 54% and 58% in SSPL and at V_{\mathrm {DD}} =0.4 and 1.0 V, respectively, in comparison with the conventional pulsed latch. |
| doi_str_mv | 10.1109/TVLSI.2022.3184410 |
| format | Article |
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As SSPL captures the data input after the clock edge, the large setup-time problem that exists in the master-slave flip-flop (MSFF) is eliminated. In addition, the transparency windows are closed immediately after successfully capturing the data input (self-shut-off), and the proposed SSPL is devoid of the large hold-time problem existing in conventional pulsed latches. According to the 7-nm FinFET postlayout simulation results, the sequencing timing overheads improved by 40% and 36% in SSPL, in comparison with the conventional MSFF at <inline-formula> <tex-math notation="LaTeX">V_{\mathrm {DD}} =0.4 </tex-math></inline-formula> and 1.0 V, respectively. Furthermore, the hold time reduced by 54% and 58% in SSPL and at <inline-formula> <tex-math notation="LaTeX">V_{\mathrm {DD}} =0.4 </tex-math></inline-formula> and 1.0 V, respectively, in comparison with the conventional pulsed latch.]]></description><identifier>ISSN: 1063-8210</identifier><identifier>EISSN: 1557-9999</identifier><identifier>DOI: 10.1109/TVLSI.2022.3184410</identifier><identifier>CODEN: ITCOB4</identifier><language>eng</language><publisher>New York: IEEE</publisher><subject>Clocks ; Flip-flop ; Latches ; low power ; low voltage ; pulsed latch ; Sequential analysis ; Simulation ; Transistors ; variation aware circuit design ; Very large scale integration ; Voltage</subject><ispartof>IEEE transactions on very large scale integration (VLSI) systems, 2022-11, Vol.30 (11), p.1728-1738</ispartof><rights>Copyright The Institute of Electrical and Electronics Engineers, Inc. (IEEE) 2022</rights><lds50>peer_reviewed</lds50><woscitedreferencessubscribed>false</woscitedreferencessubscribed><cites>FETCH-LOGICAL-c246t-2be6330675a3b6361ad44c2f6cd9c3a7929f111ee09fb4062acd4e5e960f550e3</cites><orcidid>0000-0002-7346-6739 ; 0000-0002-2723-972X</orcidid></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://ieeexplore.ieee.org/document/9812474$$EHTML$$P50$$Gieee$$H</linktohtml><link.rule.ids>314,776,780,792,27901,27902,54733</link.rule.ids><linktorsrc>$$Uhttps://ieeexplore.ieee.org/document/9812474$$EView_record_in_IEEE$$FView_record_in_$$GIEEE</linktorsrc></links><search><creatorcontrib>Park, Hyunho</creatorcontrib><creatorcontrib>Jeong, Hanwool</creatorcontrib><title>Self-Shut-Off Pulsed Latches for Minimizing Sequencing Overhead</title><title>IEEE transactions on very large scale integration (VLSI) systems</title><addtitle>TVLSI</addtitle><description><![CDATA[In this study, a self-shut-off pulsed latch (SSPL) is proposed as sequencing elements for reducing the hold time constraint. As SSPL captures the data input after the clock edge, the large setup-time problem that exists in the master-slave flip-flop (MSFF) is eliminated. In addition, the transparency windows are closed immediately after successfully capturing the data input (self-shut-off), and the proposed SSPL is devoid of the large hold-time problem existing in conventional pulsed latches. According to the 7-nm FinFET postlayout simulation results, the sequencing timing overheads improved by 40% and 36% in SSPL, in comparison with the conventional MSFF at <inline-formula> <tex-math notation="LaTeX">V_{\mathrm {DD}} =0.4 </tex-math></inline-formula> and 1.0 V, respectively. Furthermore, the hold time reduced by 54% and 58% in SSPL and at <inline-formula> <tex-math notation="LaTeX">V_{\mathrm {DD}} =0.4 </tex-math></inline-formula> and 1.0 V, respectively, in comparison with the conventional pulsed latch.]]></description><subject>Clocks</subject><subject>Flip-flop</subject><subject>Latches</subject><subject>low power</subject><subject>low voltage</subject><subject>pulsed latch</subject><subject>Sequential analysis</subject><subject>Simulation</subject><subject>Transistors</subject><subject>variation aware circuit design</subject><subject>Very large scale integration</subject><subject>Voltage</subject><issn>1063-8210</issn><issn>1557-9999</issn><fulltext>true</fulltext><rsrctype>article</rsrctype><creationdate>2022</creationdate><recordtype>article</recordtype><sourceid>RIE</sourceid><recordid>eNo9kMtOwzAQRS0EEqXwA7CJxDpl_IhTrxCqKFQKKlIKW8t1xjRVmxQ7QYKvx6UVs5m7uGcel5BrCiNKQd0t3otyNmLA2IjTsRAUTsiAZlmeqlinUYPk6ZhROCcXIawBqBAKBuS-xI1Ly1XfpXPnktd-E7BKCtPZFYbEtT55qZt6W__UzUdS4mePjd3L-Rf6FZrqkpw5E5mrYx-St-njYvKcFvOn2eShSC0TskvZEiXnIPPM8KXkkppKCMuctJWy3OSKKUcpRQTllgIkM7YSmKGS4LIMkA_J7WHuzrfxiNDpddv7Jq7ULGc5xG8yGV3s4LK-DcGj0ztfb43_1hT0Pij9F5TeB6WPQUXo5gDViPgPqDFlIhf8F2zNY2o</recordid><startdate>20221101</startdate><enddate>20221101</enddate><creator>Park, Hyunho</creator><creator>Jeong, Hanwool</creator><general>IEEE</general><general>The Institute of Electrical and Electronics Engineers, Inc. (IEEE)</general><scope>97E</scope><scope>RIA</scope><scope>RIE</scope><scope>AAYXX</scope><scope>CITATION</scope><scope>7SP</scope><scope>8FD</scope><scope>L7M</scope><orcidid>https://orcid.org/0000-0002-7346-6739</orcidid><orcidid>https://orcid.org/0000-0002-2723-972X</orcidid></search><sort><creationdate>20221101</creationdate><title>Self-Shut-Off Pulsed Latches for Minimizing Sequencing Overhead</title><author>Park, Hyunho ; Jeong, Hanwool</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-c246t-2be6330675a3b6361ad44c2f6cd9c3a7929f111ee09fb4062acd4e5e960f550e3</frbrgroupid><rsrctype>articles</rsrctype><prefilter>articles</prefilter><language>eng</language><creationdate>2022</creationdate><topic>Clocks</topic><topic>Flip-flop</topic><topic>Latches</topic><topic>low power</topic><topic>low voltage</topic><topic>pulsed latch</topic><topic>Sequential analysis</topic><topic>Simulation</topic><topic>Transistors</topic><topic>variation aware circuit design</topic><topic>Very large scale integration</topic><topic>Voltage</topic><toplevel>peer_reviewed</toplevel><toplevel>online_resources</toplevel><creatorcontrib>Park, Hyunho</creatorcontrib><creatorcontrib>Jeong, Hanwool</creatorcontrib><collection>IEEE All-Society Periodicals Package (ASPP) 2005-present</collection><collection>IEEE All-Society Periodicals Package (ASPP) 1998-Present</collection><collection>IEEE Electronic Library (IEL)</collection><collection>CrossRef</collection><collection>Electronics & Communications Abstracts</collection><collection>Technology Research Database</collection><collection>Advanced Technologies Database with Aerospace</collection><jtitle>IEEE transactions on very large scale integration (VLSI) systems</jtitle></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Park, Hyunho</au><au>Jeong, Hanwool</au><format>journal</format><genre>article</genre><ristype>JOUR</ristype><atitle>Self-Shut-Off Pulsed Latches for Minimizing Sequencing Overhead</atitle><jtitle>IEEE transactions on very large scale integration (VLSI) systems</jtitle><stitle>TVLSI</stitle><date>2022-11-01</date><risdate>2022</risdate><volume>30</volume><issue>11</issue><spage>1728</spage><epage>1738</epage><pages>1728-1738</pages><issn>1063-8210</issn><eissn>1557-9999</eissn><coden>ITCOB4</coden><abstract><![CDATA[In this study, a self-shut-off pulsed latch (SSPL) is proposed as sequencing elements for reducing the hold time constraint. As SSPL captures the data input after the clock edge, the large setup-time problem that exists in the master-slave flip-flop (MSFF) is eliminated. In addition, the transparency windows are closed immediately after successfully capturing the data input (self-shut-off), and the proposed SSPL is devoid of the large hold-time problem existing in conventional pulsed latches. According to the 7-nm FinFET postlayout simulation results, the sequencing timing overheads improved by 40% and 36% in SSPL, in comparison with the conventional MSFF at <inline-formula> <tex-math notation="LaTeX">V_{\mathrm {DD}} =0.4 </tex-math></inline-formula> and 1.0 V, respectively. Furthermore, the hold time reduced by 54% and 58% in SSPL and at <inline-formula> <tex-math notation="LaTeX">V_{\mathrm {DD}} =0.4 </tex-math></inline-formula> and 1.0 V, respectively, in comparison with the conventional pulsed latch.]]></abstract><cop>New York</cop><pub>IEEE</pub><doi>10.1109/TVLSI.2022.3184410</doi><tpages>11</tpages><orcidid>https://orcid.org/0000-0002-7346-6739</orcidid><orcidid>https://orcid.org/0000-0002-2723-972X</orcidid></addata></record> |
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| issn | 1063-8210 1557-9999 |
| language | eng |
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| source | IEEE Electronic Library (IEL) |
| subjects | Clocks Flip-flop Latches low power low voltage pulsed latch Sequential analysis Simulation Transistors variation aware circuit design Very large scale integration Voltage |
| title | Self-Shut-Off Pulsed Latches for Minimizing Sequencing Overhead |
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