High performance 35 nm gate length CMOS with NO oxynitride gate dielectric and ni SALICIDE
35 nm gate length CMOS devices with oxynitride gate dielectric and Ni SALICIDE have been fabricated to study the feasibility of achieving high performance with gate length scaling. The nitrogen profile in the gate oxynitride was optimized to reduce gate current and to prevent boron penetration in th...
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| creator | Inaba, S. Okano, K. Matsuda, S. Fujiwara, M. Hokazono, A. Adachi, K. Ohuchi, K. Suto, H. Fukui, H. Shimizu, T. Mori, S. Oguma, H. Murakoshi, A. Itani, T. Iinuma, T. Kudo, T. Shibata, H. Taniguchi, S. Matsushita, T. Magoshi, S. Watanabe, Y. Takayanagi, M. Azuma, A. Oyamatsu, H. Suguro, K. Katsumata, Y. Toyoshima, Y. Ishiuchi, H. |
| description | 35 nm gate length CMOS devices with oxynitride gate dielectric and Ni SALICIDE have been fabricated to study the feasibility of achieving high performance with gate length scaling. The nitrogen profile in the gate oxynitride was optimized to reduce gate current and to prevent boron penetration in the pFET. The thermal budget in MOL & BEOL processes was reduced to realize shallower junction depth in the S/D extension region and to suppress gate poly-Si depletion. Finally, current drives of 676 /spl mu/A//spl mu/m in nFET and 272 /spl mu/A//spl mu/m in pFET at V/sub dd/ = 0.85 V (I/sub off/ = 100 nA//spl mu/m) were achieved, which are the best values in 35 nm gate length CMOS reported to date. |
| doi_str_mv | 10.1109/IEDM.2001.979590 |
| format | Conference Proceeding |
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Technical Digest (Cat. No.01CH37224)</title><addtitle>IEDM</addtitle><description>35 nm gate length CMOS devices with oxynitride gate dielectric and Ni SALICIDE have been fabricated to study the feasibility of achieving high performance with gate length scaling. The nitrogen profile in the gate oxynitride was optimized to reduce gate current and to prevent boron penetration in the pFET. The thermal budget in MOL & BEOL processes was reduced to realize shallower junction depth in the S/D extension region and to suppress gate poly-Si depletion. Finally, current drives of 676 /spl mu/A//spl mu/m in nFET and 272 /spl mu/A//spl mu/m in pFET at V/sub dd/ = 0.85 V (I/sub off/ = 100 nA//spl mu/m) were achieved, which are the best values in 35 nm gate length CMOS reported to date.</description><subject>Boron</subject><subject>CMOS process</subject><subject>Dielectric devices</subject><subject>Fabrication</subject><subject>Implants</subject><subject>Impurities</subject><subject>Indium</subject><subject>Large scale integration</subject><subject>Nitrogen</subject><subject>Threshold voltage</subject><isbn>0780370503</isbn><isbn>9780780370500</isbn><fulltext>true</fulltext><rsrctype>conference_proceeding</rsrctype><creationdate>2001</creationdate><recordtype>conference_proceeding</recordtype><sourceid>6IE</sourceid><sourceid>RIE</sourceid><recordid>eNotjz1rwzAYhAWl0DbNXjrpD9jVZySNwUkbg1MPydQlyNJrR8VWgm1o8-9rcG-54-E4OIReKEkpJeYt3272KSOEpkYZacgdeiJKE66IJPwBLYfhm0wSUvAVe0Rfu9Cc8RX6-tJ3NjrAXOLY4caOgFuIzXjG2b484J8wpc8SX35vMYx98DB3fIAW3AQcttHjGPBhXeRZvtk-o_vatgMs_32Bju_bY7ZLivIjz9ZFErQaE1crEHolmHW1A86404Zbo5WphYTKUQPCU0lUpZkGBQy8BOU4Y0ZVziu-QK_zbACA07UPne1vp_k8_wOdHU6j</recordid><startdate>2001</startdate><enddate>2001</enddate><creator>Inaba, S.</creator><creator>Okano, K.</creator><creator>Matsuda, S.</creator><creator>Fujiwara, M.</creator><creator>Hokazono, A.</creator><creator>Adachi, K.</creator><creator>Ohuchi, K.</creator><creator>Suto, H.</creator><creator>Fukui, H.</creator><creator>Shimizu, T.</creator><creator>Mori, S.</creator><creator>Oguma, H.</creator><creator>Murakoshi, A.</creator><creator>Itani, T.</creator><creator>Iinuma, T.</creator><creator>Kudo, T.</creator><creator>Shibata, H.</creator><creator>Taniguchi, S.</creator><creator>Matsushita, T.</creator><creator>Magoshi, S.</creator><creator>Watanabe, Y.</creator><creator>Takayanagi, M.</creator><creator>Azuma, A.</creator><creator>Oyamatsu, H.</creator><creator>Suguro, K.</creator><creator>Katsumata, Y.</creator><creator>Toyoshima, Y.</creator><creator>Ishiuchi, H.</creator><general>IEEE</general><scope>6IE</scope><scope>6IH</scope><scope>CBEJK</scope><scope>RIE</scope><scope>RIO</scope></search><sort><creationdate>2001</creationdate><title>High performance 35 nm gate length CMOS with NO oxynitride gate dielectric and ni SALICIDE</title><author>Inaba, S. ; Okano, K. ; Matsuda, S. ; Fujiwara, M. ; Hokazono, A. ; Adachi, K. ; Ohuchi, K. ; Suto, H. ; Fukui, H. ; Shimizu, T. ; Mori, S. ; Oguma, H. ; Murakoshi, A. ; Itani, T. ; Iinuma, T. ; Kudo, T. ; Shibata, H. ; Taniguchi, S. ; Matsushita, T. ; Magoshi, S. ; Watanabe, Y. ; Takayanagi, M. ; Azuma, A. ; Oyamatsu, H. ; Suguro, K. ; Katsumata, Y. ; Toyoshima, Y. ; Ishiuchi, H.</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-i87t-cf7e48642acfce323c893a9879f45ebc19e4d1507b828e7e2ed5e7c32297bcd73</frbrgroupid><rsrctype>conference_proceedings</rsrctype><prefilter>conference_proceedings</prefilter><language>eng</language><creationdate>2001</creationdate><topic>Boron</topic><topic>CMOS process</topic><topic>Dielectric devices</topic><topic>Fabrication</topic><topic>Implants</topic><topic>Impurities</topic><topic>Indium</topic><topic>Large scale integration</topic><topic>Nitrogen</topic><topic>Threshold voltage</topic><toplevel>online_resources</toplevel><creatorcontrib>Inaba, S.</creatorcontrib><creatorcontrib>Okano, K.</creatorcontrib><creatorcontrib>Matsuda, S.</creatorcontrib><creatorcontrib>Fujiwara, M.</creatorcontrib><creatorcontrib>Hokazono, A.</creatorcontrib><creatorcontrib>Adachi, K.</creatorcontrib><creatorcontrib>Ohuchi, K.</creatorcontrib><creatorcontrib>Suto, H.</creatorcontrib><creatorcontrib>Fukui, H.</creatorcontrib><creatorcontrib>Shimizu, T.</creatorcontrib><creatorcontrib>Mori, S.</creatorcontrib><creatorcontrib>Oguma, H.</creatorcontrib><creatorcontrib>Murakoshi, A.</creatorcontrib><creatorcontrib>Itani, T.</creatorcontrib><creatorcontrib>Iinuma, T.</creatorcontrib><creatorcontrib>Kudo, T.</creatorcontrib><creatorcontrib>Shibata, H.</creatorcontrib><creatorcontrib>Taniguchi, S.</creatorcontrib><creatorcontrib>Matsushita, T.</creatorcontrib><creatorcontrib>Magoshi, S.</creatorcontrib><creatorcontrib>Watanabe, Y.</creatorcontrib><creatorcontrib>Takayanagi, M.</creatorcontrib><creatorcontrib>Azuma, A.</creatorcontrib><creatorcontrib>Oyamatsu, H.</creatorcontrib><creatorcontrib>Suguro, K.</creatorcontrib><creatorcontrib>Katsumata, Y.</creatorcontrib><creatorcontrib>Toyoshima, Y.</creatorcontrib><creatorcontrib>Ishiuchi, H.</creatorcontrib><collection>IEEE Electronic Library (IEL) Conference Proceedings</collection><collection>IEEE Proceedings Order Plan (POP) 1998-present by volume</collection><collection>IEEE Xplore All Conference Proceedings</collection><collection>IEEE Electronic Library (IEL)</collection><collection>IEEE Proceedings Order Plans (POP) 1998-present</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Inaba, S.</au><au>Okano, K.</au><au>Matsuda, S.</au><au>Fujiwara, M.</au><au>Hokazono, A.</au><au>Adachi, K.</au><au>Ohuchi, K.</au><au>Suto, H.</au><au>Fukui, H.</au><au>Shimizu, T.</au><au>Mori, S.</au><au>Oguma, H.</au><au>Murakoshi, A.</au><au>Itani, T.</au><au>Iinuma, T.</au><au>Kudo, T.</au><au>Shibata, H.</au><au>Taniguchi, S.</au><au>Matsushita, T.</au><au>Magoshi, S.</au><au>Watanabe, Y.</au><au>Takayanagi, M.</au><au>Azuma, A.</au><au>Oyamatsu, H.</au><au>Suguro, K.</au><au>Katsumata, Y.</au><au>Toyoshima, Y.</au><au>Ishiuchi, H.</au><format>book</format><genre>proceeding</genre><ristype>CONF</ristype><atitle>High performance 35 nm gate length CMOS with NO oxynitride gate dielectric and ni SALICIDE</atitle><btitle>International Electron Devices Meeting. Technical Digest (Cat. No.01CH37224)</btitle><stitle>IEDM</stitle><date>2001</date><risdate>2001</risdate><spage>29.6.1</spage><epage>29.6.4</epage><pages>29.6.1-29.6.4</pages><isbn>0780370503</isbn><isbn>9780780370500</isbn><abstract>35 nm gate length CMOS devices with oxynitride gate dielectric and Ni SALICIDE have been fabricated to study the feasibility of achieving high performance with gate length scaling. The nitrogen profile in the gate oxynitride was optimized to reduce gate current and to prevent boron penetration in the pFET. The thermal budget in MOL & BEOL processes was reduced to realize shallower junction depth in the S/D extension region and to suppress gate poly-Si depletion. Finally, current drives of 676 /spl mu/A//spl mu/m in nFET and 272 /spl mu/A//spl mu/m in pFET at V/sub dd/ = 0.85 V (I/sub off/ = 100 nA//spl mu/m) were achieved, which are the best values in 35 nm gate length CMOS reported to date.</abstract><pub>IEEE</pub><doi>10.1109/IEDM.2001.979590</doi></addata></record> |
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| identifier | ISBN: 0780370503 |
| ispartof | International Electron Devices Meeting. Technical Digest (Cat. No.01CH37224), 2001, p.29.6.1-29.6.4 |
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| language | eng |
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| source | IEEE Electronic Library (IEL) Conference Proceedings |
| subjects | Boron CMOS process Dielectric devices Fabrication Implants Impurities Indium Large scale integration Nitrogen Threshold voltage |
| title | High performance 35 nm gate length CMOS with NO oxynitride gate dielectric and ni SALICIDE |
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