CMOS device optimization for mixed-signal technologies

CMOS device optimization for mixed-signal technologies

This paper studies the suitability of CMOS device technology for mixed-signal applications. The currently proposed scaling scenario's for CMOS technologies lead to strong degradation of analog transistor performance. As a result the combined optimization of digital and analog devices for system...

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Hauptverfasser: Stolk, P.A., Tuinhout, H.P., Duffy, R., Augendre, E., Bellefroid, L.P., Bolt, M.J.B., Croon, J., Dachs, C.J.J., Huisman, F.R.J., Moonen, A.J., Ponomarev, Y.V., Roes, R.F.M., Da Rold, M., Seevinck, E., Sreerambhatla, K.N., Surdeanu, R., Velghe, R.M.D.A., Vertregt, M., Webster, M.N., van Winkelhoff, N.K.J., Zegers-Van Duijnhoven, A.T.A.
Format: Tagungsbericht
Sprache:eng
Schlagworte:
CMOS process
CMOS technology
Fasteners
Fluctuations
Implants
Laboratories
Lips
MOS devices
Random access memory
Threshold voltage
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Beschreibung
Zusammenfassung:This paper studies the suitability of CMOS device technology for mixed-signal applications. The currently proposed scaling scenario's for CMOS technologies lead to strong degradation of analog transistor performance. As a result the combined optimization of digital and analog devices for system-on-a-chip applications will require increasingly elaborate process modifications. New device solutions such as metal gate integration and asymmetric (source-side-only) workfunction modification offer process options for future mixed-signal CMOS applications.
DOI:10.1109/IEDM.2001.979469