A 22.2-GHz Injection-Locked Frequency Tripler Featuring Dual Injection and 39.4% Locking Range
This article proposes a dual injection locking technique to significantly enhance the locking range (LR) of the injection-locked frequency tripler (ILFT). Compared with the conventional circuit topology that typically suffers from limited LR due to G_{m} degeneration, the proposed technique employ...
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| Veröffentlicht in: | IEEE transactions on microwave theory and techniques 2022-07, Vol.70 (7), p.3548-3556 |
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| container_end_page | 3556 |
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| container_issue | 7 |
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| container_title | IEEE transactions on microwave theory and techniques |
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| creator | Wan, Cao Wu, Liang Zhu, Haoshen Xu, Taotao Xue, Quan |
| description | This article proposes a dual injection locking technique to significantly enhance the locking range (LR) of the injection-locked frequency tripler (ILFT). Compared with the conventional circuit topology that typically suffers from limited LR due to G_{m} degeneration, the proposed technique employs drain injection and source injection together to increase the LR, with power consumption increased only a little. Fabricated in standard CMOS 65-nm technology, the ILFT prototype measures a 39.4% LR at 0-dBm input power while consuming 8.16 mW from a 1-V supply. The chip area is 0.32 mm 2 including the pads. The proposed ILFT is applicable for local oscillation generation in the 5G transceiver. |
| doi_str_mv | 10.1109/TMTT.2022.3175212 |
| format | Article |
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Compared with the conventional circuit topology that typically suffers from limited LR due to <inline-formula> <tex-math notation="LaTeX">G_{m} </tex-math></inline-formula> degeneration, the proposed technique employs drain injection and source injection together to increase the LR, with power consumption increased only a little. Fabricated in standard CMOS 65-nm technology, the ILFT prototype measures a 39.4% LR at 0-dBm input power while consuming 8.16 mW from a 1-V supply. The chip area is 0.32 mm 2 including the pads. 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Compared with the conventional circuit topology that typically suffers from limited LR due to <inline-formula> <tex-math notation="LaTeX">G_{m} </tex-math></inline-formula> degeneration, the proposed technique employs drain injection and source injection together to increase the LR, with power consumption increased only a little. Fabricated in standard CMOS 65-nm technology, the ILFT prototype measures a 39.4% LR at 0-dBm input power while consuming 8.16 mW from a 1-V supply. The chip area is 0.32 mm 2 including the pads. The proposed ILFT is applicable for local oscillation generation in the 5G transceiver.</description><subject>5G mobile communication</subject><subject>Circuits</subject><subject>Degeneration</subject><subject>Dual injection</subject><subject>Frequency locking</subject><subject>Gm degeneration</subject><subject>Harmonic analysis</subject><subject>Inductors</subject><subject>injection current enhancement</subject><subject>injection locking</subject><subject>injection-locked frequency tripler (ILFT)</subject><subject>Phase locked loops</subject><subject>Power consumption</subject><subject>Power demand</subject><subject>Tail</subject><subject>Topology</subject><subject>Transceivers</subject><subject>wideband</subject><issn>0018-9480</issn><issn>1557-9670</issn><fulltext>true</fulltext><rsrctype>article</rsrctype><creationdate>2022</creationdate><recordtype>article</recordtype><sourceid>RIE</sourceid><recordid>eNpFkE1LAzEQhoMoWKs_QLwExOOu-dhskmOp9gMqgqxXQ5rMlq01W7O7h_rr3aVFT8Mw7zMzPAjdUpJSSvRj8VIUKSOMpZxKwSg7QyMqhEx0Lsk5GhFCVaIzRS7RVdNs-zYTRI3QxwT3DEvmix-8DFtwbVWHZFW7T_B4FuG7g-AOuIjVfgcRz8C2XazCBj91dvdPYBs85jrNHvDADoE3GzZwjS5Ku2vg5lTH6H32XEwXyep1vpxOVoljjLfJOvNaCS8VdT5fC50J7ktthbZEZiKT4IBL5nmZa0907l2uBShHgTsnoOR8jO6Pe_ex7l9uWrOtuxj6k4blimkqtdR9ih5TLtZNE6E0-1h92XgwlJhBoxk0mkGjOWnsmbsjUwHAX15L1Q9z_gsmmWwg</recordid><startdate>20220701</startdate><enddate>20220701</enddate><creator>Wan, Cao</creator><creator>Wu, Liang</creator><creator>Zhu, Haoshen</creator><creator>Xu, Taotao</creator><creator>Xue, Quan</creator><general>IEEE</general><general>The Institute of Electrical and Electronics Engineers, Inc. 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Compared with the conventional circuit topology that typically suffers from limited LR due to <inline-formula> <tex-math notation="LaTeX">G_{m} </tex-math></inline-formula> degeneration, the proposed technique employs drain injection and source injection together to increase the LR, with power consumption increased only a little. Fabricated in standard CMOS 65-nm technology, the ILFT prototype measures a 39.4% LR at 0-dBm input power while consuming 8.16 mW from a 1-V supply. The chip area is 0.32 mm 2 including the pads. The proposed ILFT is applicable for local oscillation generation in the 5G transceiver.</abstract><cop>New York</cop><pub>IEEE</pub><doi>10.1109/TMTT.2022.3175212</doi><tpages>9</tpages><orcidid>https://orcid.org/0000-0001-7972-4789</orcidid><orcidid>https://orcid.org/0000-0003-2944-3035</orcidid><orcidid>https://orcid.org/0000-0002-4226-2127</orcidid><orcidid>https://orcid.org/0000-0001-7094-606X</orcidid></addata></record> |
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| ispartof | IEEE transactions on microwave theory and techniques, 2022-07, Vol.70 (7), p.3548-3556 |
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| subjects | 5G mobile communication Circuits Degeneration Dual injection Frequency locking Gm degeneration Harmonic analysis Inductors injection current enhancement injection locking injection-locked frequency tripler (ILFT) Phase locked loops Power consumption Power demand Tail Topology Transceivers wideband |
| title | A 22.2-GHz Injection-Locked Frequency Tripler Featuring Dual Injection and 39.4% Locking Range |
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