Top-Gated MoS₂ Negative-Capacitance Transistors Fabricated by an Integral-Transfer of Pulsed Laser Deposited HfZrO₂ on Mica

Top-gated (TG) molybdenum disulfide (MoS 2 ) field-effect transistors (FETs) suffer from surface damage, unintentional doping, and other defects introduced to the MoS 2 channel during the direct deposition of the gate dielectric. In addition, the delicate MoS 2 cannot withstand high-temperature proc...

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Veröffentlicht in:IEEE transactions on electron devices 2022-06, Vol.69 (6), p.3477-3482
Hauptverfasser: Zou, Xiao, Zou, Jiyue, Liu, Lu, Wang, Hongjiu, Xu, Jing-Ping
Format: Artikel
Sprache:eng
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Zusammenfassung:Top-gated (TG) molybdenum disulfide (MoS 2 ) field-effect transistors (FETs) suffer from surface damage, unintentional doping, and other defects introduced to the MoS 2 channel during the direct deposition of the gate dielectric. In addition, the delicate MoS 2 cannot withstand high-temperature processing or annealing. To overcome these obstacles, a novel path to prepare TG MoS 2 negative-capacitance (NC) FETs is proposed in this study. A ferroelectric HfZrO 2 (HZO) is first deposited on the mica flake by pulsed laser deposition (PLD) and then annealed by rapid thermal processing. Subsequently, the HZO/mica stack is integrally transferred onto the MoS 2 surface, without needing to expose the MoS 2 flake to harsh temperatures or PLD environments. TG multilayered MoS 2 NCFETs with the HZO/mica stack are fabricated and demonstrate stable NC effects and superior performance with a subthreshold swing (SS) of 49 mV/dec, ON/OFF current ratio above 10 7 , and anticlockwise hysteresis voltages of 64 mV, which are attributed to vital contributions from the damage-free mica/MoS 2 van der Waals heterojunction interface and reasonable capacitance matching between the mica dielectric and the ferroelectric HZO film. Moreover, the experimental results of the dual-gate MoS 2 transistor modulated by the bottom gate show that a positive bottom-gate bias can increase drain current and decrease hysteresis voltage, and a negative bottom-gate bias can reduce SS. Therefore, the proposed approach changes the current situation that the PLD method is hardly used to fabricate TG MoS 2 transistors and opens a new window for nanoelectronics.
ISSN:0018-9383
1557-9646
DOI:10.1109/TED.2022.3170862