A new test algorithm for bit-line sensitive faults in super high- density memories

As the density of memories increases, unwanted interference between cells and coupling noise between bit-lines are increased and testing high density memories for a high degree of fault coverage can require either a relatively large number of test vectors or a significant amount of additional test c...

Ausführliche Beschreibung

Bibliographische Detailangaben

Hauptverfasser:	Dong-Chual Kang, Jong-Hwa Lee, Sang-Bock Cho
Format:	Tagungsbericht
Sprache:	eng
Schlagworte:	Automatic testing Automation Capacitance Capacitors Circuit faults Circuit testing Crosstalk Electronic equipment testing Fault detection Voltage
Online-Zugang:	Volltext bestellen
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