A Self-Refreshable Bit-Cell for Single-Cycle Refreshing of Embedded Memories
Power supply voltage reduction is a primary enabler for sustaining the increasing demand for ultra-low power processors. On-die memories, which are traditionally implemented by SRAM, stop functioning properly when the supply voltage is scaled down aggressively; hence, embedded DRAM (eDRAM) bit-cells...
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Veröffentlicht in: | IEEE transactions on computers 2023-02, Vol.72 (2), p.513-519 |
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description | Power supply voltage reduction is a primary enabler for sustaining the increasing demand for ultra-low power processors. On-die memories, which are traditionally implemented by SRAM, stop functioning properly when the supply voltage is scaled down aggressively; hence, embedded DRAM (eDRAM) bit-cells are used instead. These bit-cells leak their data strongly in one direction, whereas the leakage in the opposite direction is considerably lower. Due to their intrinsic limited Data Retention Time (DRT), these memories require power-hungry refreshing, which degrades performance. In an attempt to extend the DRT of a bit-cell, theoretically to infinity, compounds of various types of storage nodes in a single bit-cell, storing the datum and its complement, were examined here. A rigorous proof shows that under realistic leakage models, there is an inherent incompleteness preventing the proper readout and decision of the stored value after a certain time. Adopting the idea of dual-polarity complementary storage nodes, a new eDRAM self-refreshable bit-cell is proposed that yields a considerably extended DRT. The dual-polarity property enables the refreshing of an entire memory array in a single clock cycle, thus almost nullifying the unavoidable performance loss occurred by row-by-row ordinary power-hungry refreshing. |
doi_str_mv | 10.1109/TC.2022.3158481 |
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On-die memories, which are traditionally implemented by SRAM, stop functioning properly when the supply voltage is scaled down aggressively; hence, embedded DRAM (eDRAM) bit-cells are used instead. These bit-cells leak their data strongly in one direction, whereas the leakage in the opposite direction is considerably lower. Due to their intrinsic limited Data Retention Time (DRT), these memories require power-hungry refreshing, which degrades performance. In an attempt to extend the DRT of a bit-cell, theoretically to infinity, compounds of various types of storage nodes in a single bit-cell, storing the datum and its complement, were examined here. A rigorous proof shows that under realistic leakage models, there is an inherent incompleteness preventing the proper readout and decision of the stored value after a certain time. Adopting the idea of dual-polarity complementary storage nodes, a new eDRAM self-refreshable bit-cell is proposed that yields a considerably extended DRT. The dual-polarity property enables the refreshing of an entire memory array in a single clock cycle, thus almost nullifying the unavoidable performance loss occurred by row-by-row ordinary power-hungry refreshing.</description><identifier>ISSN: 0018-9340</identifier><identifier>EISSN: 1557-9956</identifier><identifier>DOI: 10.1109/TC.2022.3158481</identifier><identifier>CODEN: ITCOB4</identifier><language>eng</language><publisher>New York: IEEE</publisher><subject>dynamic memories ; embedded memories ; Leakage ; Logic gates ; Memory design ; Memory management ; memory technologies ; Nodes ; Performance degradation ; Power management ; Power supplies ; Program processors ; Random access memory ; refreshing ; Storage ; Transistors ; Voltage ; Voltage reduction</subject><ispartof>IEEE transactions on computers, 2023-02, Vol.72 (2), p.513-519</ispartof><rights>Copyright The Institute of Electrical and Electronics Engineers, Inc. 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On-die memories, which are traditionally implemented by SRAM, stop functioning properly when the supply voltage is scaled down aggressively; hence, embedded DRAM (eDRAM) bit-cells are used instead. These bit-cells leak their data strongly in one direction, whereas the leakage in the opposite direction is considerably lower. Due to their intrinsic limited Data Retention Time (DRT), these memories require power-hungry refreshing, which degrades performance. In an attempt to extend the DRT of a bit-cell, theoretically to infinity, compounds of various types of storage nodes in a single bit-cell, storing the datum and its complement, were examined here. A rigorous proof shows that under realistic leakage models, there is an inherent incompleteness preventing the proper readout and decision of the stored value after a certain time. Adopting the idea of dual-polarity complementary storage nodes, a new eDRAM self-refreshable bit-cell is proposed that yields a considerably extended DRT. The dual-polarity property enables the refreshing of an entire memory array in a single clock cycle, thus almost nullifying the unavoidable performance loss occurred by row-by-row ordinary power-hungry refreshing.</description><subject>dynamic memories</subject><subject>embedded memories</subject><subject>Leakage</subject><subject>Logic gates</subject><subject>Memory design</subject><subject>Memory management</subject><subject>memory technologies</subject><subject>Nodes</subject><subject>Performance degradation</subject><subject>Power management</subject><subject>Power supplies</subject><subject>Program processors</subject><subject>Random access memory</subject><subject>refreshing</subject><subject>Storage</subject><subject>Transistors</subject><subject>Voltage</subject><subject>Voltage reduction</subject><issn>0018-9340</issn><issn>1557-9956</issn><fulltext>true</fulltext><rsrctype>article</rsrctype><creationdate>2023</creationdate><recordtype>article</recordtype><sourceid>RIE</sourceid><recordid>eNo9kM1Lw0AQxRdRsFbPHrwEPG87-5nssYb6ARXB1vOSbGY1JW3qbnrof--WFpnDwMzvzTweIfcMJoyBma7KCQfOJ4KpQhbsgoyYUjk1RulLMgJgBTVCwjW5iXENAJqDGZHFLFti5-kn-oDxp6o7zJ7agZbYdZnvQ7Zst98d0vLg0uZMpVHW-2y-qbFpsMnecdOHFuMtufJVF_Hu3Mfk63m-Kl_p4uPlrZwtqONSDFQli6zmtc4r6bhSxjmmUdWVaWrhwAheeAeYKnnnRmjpITHS81ryvCjEmDye7u5C_7vHONh1vw_b9NLyXGvNuVCQqOmJcqGPMaC3u9BuqnCwDOwxMrsq7TEye44sKR5OihYR_2mTC66lFH_KvWTa</recordid><startdate>20230201</startdate><enddate>20230201</enddate><creator>Frankel, Binyamin</creator><creator>Wimer, Shmuel</creator><general>IEEE</general><general>The Institute of Electrical and Electronics Engineers, Inc. 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On-die memories, which are traditionally implemented by SRAM, stop functioning properly when the supply voltage is scaled down aggressively; hence, embedded DRAM (eDRAM) bit-cells are used instead. These bit-cells leak their data strongly in one direction, whereas the leakage in the opposite direction is considerably lower. Due to their intrinsic limited Data Retention Time (DRT), these memories require power-hungry refreshing, which degrades performance. In an attempt to extend the DRT of a bit-cell, theoretically to infinity, compounds of various types of storage nodes in a single bit-cell, storing the datum and its complement, were examined here. A rigorous proof shows that under realistic leakage models, there is an inherent incompleteness preventing the proper readout and decision of the stored value after a certain time. Adopting the idea of dual-polarity complementary storage nodes, a new eDRAM self-refreshable bit-cell is proposed that yields a considerably extended DRT. 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subjects | dynamic memories embedded memories Leakage Logic gates Memory design Memory management memory technologies Nodes Performance degradation Power management Power supplies Program processors Random access memory refreshing Storage Transistors Voltage Voltage reduction |
title | A Self-Refreshable Bit-Cell for Single-Cycle Refreshing of Embedded Memories |
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