EM SCA White-Box Analysis-Based Reduced Leakage Cell Design and Presilicon Evaluation
This work presents a white-box modeling of the electromagnetic (EM) leakage from an integrated circuit (IC) to develop EM side-channel analysis (SCA)-aware design techniques. A new digital library cell layout design technique is proposed to minimize the EM leakage and is evaluated using a high-frequ...
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| Veröffentlicht in: | IEEE transactions on computer-aided design of integrated circuits and systems 2022-11, Vol.41 (11), p.4927-4938 |
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| container_issue | 11 |
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| container_title | IEEE transactions on computer-aided design of integrated circuits and systems |
| container_volume | 41 |
| creator | Das, Debayan Nath, Mayukh Chatterjee, Baibhab Kumar, Raghavan Liu, Xiaosen Krishnamurthy, Harish Sastry, Manoj Mathew, Sanu Ghosh, Santosh Sen, Shreyas |
| description | This work presents a white-box modeling of the electromagnetic (EM) leakage from an integrated circuit (IC) to develop EM side-channel analysis (SCA)-aware design techniques. A new digital library cell layout design technique is proposed to minimize the EM leakage and is evaluated using a high-frequency structure simulator (HFSS)-based framework. Backed by our physics-based understanding of EM radiation, the proposed double-row power grid-based digital cell layout design shows >5\times reduction in the EM SCA leakage compared to the traditional digital logic gate layout design. Furthermore, exploiting the magneto-quasistatic (MQS) regime of operation of the EM leakage from the CMOS circuits, the HFSS-based framework is utilized to develop a pre-silicon (Si) EM SCA evaluation technique to assess the vulnerability of cryptographic implementations against such attacks during the design phase itself. |
| doi_str_mv | 10.1109/TCAD.2022.3144369 |
| format | Article |
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A new digital library cell layout design technique is proposed to minimize the EM leakage and is evaluated using a high-frequency structure simulator (HFSS)-based framework. Backed by our physics-based understanding of EM radiation, the proposed double-row power grid-based digital cell layout design shows <inline-formula> <tex-math notation="LaTeX">>5\times </tex-math></inline-formula> reduction in the EM SCA leakage compared to the traditional digital logic gate layout design. Furthermore, exploiting the magneto-quasistatic (MQS) regime of operation of the EM leakage from the CMOS circuits, the HFSS-based framework is utilized to develop a pre-silicon (Si) EM SCA evaluation technique to assess the vulnerability of cryptographic implementations against such attacks during the design phase itself.</description><identifier>ISSN: 0278-0070</identifier><identifier>EISSN: 1937-4151</identifier><identifier>DOI: 10.1109/TCAD.2022.3144369</identifier><identifier>CODEN: ITCSDI</identifier><language>eng</language><publisher>New York: IEEE</publisher><subject>Analytical models ; Circuit design ; Cryptography ; Design analysis ; Digital systems ; Electromagnetic (EM) side-channel attack ; Evaluation ; Integrated circuit modeling ; Integrated circuits ; Layout ; Layouts ; Leakage ; Logic circuits ; logic gate layout design ; Logic gates ; power grid ; Power grids ; presilicon EM side-channel analysis (SCA) evaluation ; Silicon ; white-box modeling</subject><ispartof>IEEE transactions on computer-aided design of integrated circuits and systems, 2022-11, Vol.41 (11), p.4927-4938</ispartof><rights>Copyright The Institute of Electrical and Electronics Engineers, Inc. (IEEE) 2022</rights><lds50>peer_reviewed</lds50><woscitedreferencessubscribed>false</woscitedreferencessubscribed><citedby>FETCH-LOGICAL-c293t-f871cac9797efa7d68c0d003ca51f677e1b7566d68cbbbb6a54424179fedbc883</citedby><cites>FETCH-LOGICAL-c293t-f871cac9797efa7d68c0d003ca51f677e1b7566d68cbbbb6a54424179fedbc883</cites><orcidid>0000-0003-1344-7533 ; 0000-0003-2767-215X ; 0000-0001-5566-8946 ; 0000-0002-2688-281X ; 0000-0001-5927-8339 ; 0000-0002-0305-6048 ; 0000-0001-7399-1886 ; 0000-0003-1843-0124</orcidid></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://ieeexplore.ieee.org/document/9684545$$EHTML$$P50$$Gieee$$H</linktohtml><link.rule.ids>314,777,781,793,27905,27906,54739</link.rule.ids><linktorsrc>$$Uhttps://ieeexplore.ieee.org/document/9684545$$EView_record_in_IEEE$$FView_record_in_$$GIEEE</linktorsrc></links><search><creatorcontrib>Das, Debayan</creatorcontrib><creatorcontrib>Nath, Mayukh</creatorcontrib><creatorcontrib>Chatterjee, Baibhab</creatorcontrib><creatorcontrib>Kumar, Raghavan</creatorcontrib><creatorcontrib>Liu, Xiaosen</creatorcontrib><creatorcontrib>Krishnamurthy, Harish</creatorcontrib><creatorcontrib>Sastry, Manoj</creatorcontrib><creatorcontrib>Mathew, Sanu</creatorcontrib><creatorcontrib>Ghosh, Santosh</creatorcontrib><creatorcontrib>Sen, Shreyas</creatorcontrib><title>EM SCA White-Box Analysis-Based Reduced Leakage Cell Design and Presilicon Evaluation</title><title>IEEE transactions on computer-aided design of integrated circuits and systems</title><addtitle>TCAD</addtitle><description>This work presents a white-box modeling of the electromagnetic (EM) leakage from an integrated circuit (IC) to develop EM side-channel analysis (SCA)-aware design techniques. A new digital library cell layout design technique is proposed to minimize the EM leakage and is evaluated using a high-frequency structure simulator (HFSS)-based framework. Backed by our physics-based understanding of EM radiation, the proposed double-row power grid-based digital cell layout design shows <inline-formula> <tex-math notation="LaTeX">>5\times </tex-math></inline-formula> reduction in the EM SCA leakage compared to the traditional digital logic gate layout design. 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| ispartof | IEEE transactions on computer-aided design of integrated circuits and systems, 2022-11, Vol.41 (11), p.4927-4938 |
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| language | eng |
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| source | IEEE Electronic Library (IEL) |
| subjects | Analytical models Circuit design Cryptography Design analysis Digital systems Electromagnetic (EM) side-channel attack Evaluation Integrated circuit modeling Integrated circuits Layout Layouts Leakage Logic circuits logic gate layout design Logic gates power grid Power grids presilicon EM side-channel analysis (SCA) evaluation Silicon white-box modeling |
| title | EM SCA White-Box Analysis-Based Reduced Leakage Cell Design and Presilicon Evaluation |
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