An 80/20-MHz 160-mW multimedia processor integrated with embedded DRAM, MPEG-4 accelerator and 3-D rendering engine for mobile applications

A low-power multimedia processor for mobile applications is presented. An 80-MHz 32-b RISC with enhanced multiplier, two 20-MHz hardware accelerators with 7.125-Mb embedded DRAM for MPEG-4 visual SP@L1 decoding and 3-D graphics processing, 2-kB dual-port SRAM, and peripheral blocks are integrated to...

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Veröffentlicht in:	IEEE journal of solid-state circuits 2001-11, Vol.36 (11), p.1758-1767
Hauptverfasser:	Yoon, Chi-Weon, Woo, Ramchan, Kook, Jeengheon, Lee, Se-Joong, Lee, Kangmin, Yeo, Hoi-Jun
Format:	Artikel
Sprache:	eng
Schlagworte:	Accelerators Circuits Decoding Dynamic random access memory Energy consumption Graphics Hardware Logic Microprocessors MPEG 4 Standard Power consumption Random access memory Reduced instruction set computing Rendering Rendering (computer graphics)
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