An 80/20-MHz 160-mW multimedia processor integrated with embedded DRAM, MPEG-4 accelerator and 3-D rendering engine for mobile applications
A low-power multimedia processor for mobile applications is presented. An 80-MHz 32-b RISC with enhanced multiplier, two 20-MHz hardware accelerators with 7.125-Mb embedded DRAM for MPEG-4 visual SP@L1 decoding and 3-D graphics processing, 2-kB dual-port SRAM, and peripheral blocks are integrated to...
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| Veröffentlicht in: | IEEE journal of solid-state circuits 2001-11, Vol.36 (11), p.1758-1767 |
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| container_end_page | 1767 |
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| container_issue | 11 |
| container_start_page | 1758 |
| container_title | IEEE journal of solid-state circuits |
| container_volume | 36 |
| creator | Yoon, Chi-Weon Woo, Ramchan Kook, Jeengheon Lee, Se-Joong Lee, Kangmin Yeo, Hoi-Jun |
| description | A low-power multimedia processor for mobile applications is presented. An 80-MHz 32-b RISC with enhanced multiplier, two 20-MHz hardware accelerators with 7.125-Mb embedded DRAM for MPEG-4 visual SP@L1 decoding and 3-D graphics processing, 2-kB dual-port SRAM, and peripheral blocks are integrated together on a single chip, MPEG-4 SP@L1 video decoding and 3-D graphics rendering with a 16-b depth-buffer alpha-blending double-buffering and gouraud-shading features at 2, 2-Mpolygons/s speed are realized with the help of the dedicated hardware accelerators/ The architecture of the processor is optimized in terms of power consumption and performance, and various low-power circuit techniques are adopted in each hardware block. The chip is implemented using 0.18-/spl mu/m embedded memory logic (EML) technology. Its area is 84 mm/sup 2/, and power consumption is 160 mW when all of the functions are activated. |
| doi_str_mv | 10.1109/4.962299 |
| format | Article |
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(IEEE) 2001</rights><lds50>peer_reviewed</lds50><woscitedreferencessubscribed>false</woscitedreferencessubscribed><citedby>FETCH-LOGICAL-c365t-659bdd28a612b0d882ef5e6c1d58764780e91f45a77c61b92f40980323c233383</citedby><cites>FETCH-LOGICAL-c365t-659bdd28a612b0d882ef5e6c1d58764780e91f45a77c61b92f40980323c233383</cites></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://ieeexplore.ieee.org/document/962299$$EHTML$$P50$$Gieee$$H</linktohtml><link.rule.ids>314,776,780,792,27903,27904,54737</link.rule.ids><linktorsrc>$$Uhttps://ieeexplore.ieee.org/document/962299$$EView_record_in_IEEE$$FView_record_in_$$GIEEE</linktorsrc></links><search><creatorcontrib>Yoon, Chi-Weon</creatorcontrib><creatorcontrib>Woo, Ramchan</creatorcontrib><creatorcontrib>Kook, Jeengheon</creatorcontrib><creatorcontrib>Lee, Se-Joong</creatorcontrib><creatorcontrib>Lee, Kangmin</creatorcontrib><creatorcontrib>Yeo, Hoi-Jun</creatorcontrib><title>An 80/20-MHz 160-mW multimedia processor integrated with embedded DRAM, MPEG-4 accelerator and 3-D rendering engine for mobile applications</title><title>IEEE journal of solid-state circuits</title><addtitle>JSSC</addtitle><description>A low-power multimedia processor for mobile applications is presented. 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An 80-MHz 32-b RISC with enhanced multiplier, two 20-MHz hardware accelerators with 7.125-Mb embedded DRAM for MPEG-4 visual SP@L1 decoding and 3-D graphics processing, 2-kB dual-port SRAM, and peripheral blocks are integrated together on a single chip, MPEG-4 SP@L1 video decoding and 3-D graphics rendering with a 16-b depth-buffer alpha-blending double-buffering and gouraud-shading features at 2, 2-Mpolygons/s speed are realized with the help of the dedicated hardware accelerators/ The architecture of the processor is optimized in terms of power consumption and performance, and various low-power circuit techniques are adopted in each hardware block. The chip is implemented using 0.18-/spl mu/m embedded memory logic (EML) technology. Its area is 84 mm/sup 2/, and power consumption is 160 mW when all of the functions are activated.</abstract><cop>New York</cop><pub>IEEE</pub><doi>10.1109/4.962299</doi><tpages>10</tpages></addata></record> |
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| identifier | ISSN: 0018-9200 |
| ispartof | IEEE journal of solid-state circuits, 2001-11, Vol.36 (11), p.1758-1767 |
| issn | 0018-9200 1558-173X |
| language | eng |
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| source | IEEE Electronic Library (IEL) |
| subjects | Accelerators Circuits Decoding Dynamic random access memory Energy consumption Graphics Hardware Logic Microprocessors MPEG 4 Standard Power consumption Random access memory Reduced instruction set computing Rendering Rendering (computer graphics) |
| title | An 80/20-MHz 160-mW multimedia processor integrated with embedded DRAM, MPEG-4 accelerator and 3-D rendering engine for mobile applications |
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