A 0.0285-mm2 0.68-pJ/bit Single-Loop Full-Rate Bang-Bang CDR Without Reference and Separate FD Pulling Off an 8.2-Gb/s/μs Acquisition Speed of the PAM-4 Input in 28-nm CMOS
This article reports a single-loop full-rate bang-bang clock and data recovery (BBCDR) circuit supporting a four-level pulse amplitude modulation (PAM-4) pattern. We eliminate both the reference and the separate frequency detector (FD) by deliberately adding two fixed strobe points in the bang-bang...
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| Veröffentlicht in: | IEEE journal of solid-state circuits 2022-02, Vol.57 (2), p.546-561 |
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| container_title | IEEE journal of solid-state circuits |
| container_volume | 57 |
| creator | Zhao, Xiaoteng Chen, Yong Mak, Pui-In Martins, Rui P. |
| description | This article reports a single-loop full-rate bang-bang clock and data recovery (BBCDR) circuit supporting a four-level pulse amplitude modulation (PAM-4) pattern. We eliminate both the reference and the separate frequency detector (FD) by deliberately adding two fixed strobe points in the bang-bang phase detector (BBPD) curve via a clock-selection scheme. As such, we can achieve a wide frequency-capture range in a single-sided FD polarity. The BBPD also incorporates a hybrid control circuit to automate the frequency acquisition over a wide frequency range. Prototyped in a 28-nm CMOS, the proposed BBCDR occupies a tiny area of 0.0285 mm 2 and exhibits a 23-to-29-Gb/s capture range. The acquisition speed [8.2 Gb/s/ \mu \text{s} ] and energy efficiency (0.68 pJ/bit) compare favorably with the state of the art. |
| doi_str_mv | 10.1109/JSSC.2021.3113773 |
| format | Article |
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We eliminate both the reference and the separate frequency detector (FD) by deliberately adding two fixed strobe points in the bang-bang phase detector (BBPD) curve via a clock-selection scheme. As such, we can achieve a wide frequency-capture range in a single-sided FD polarity. The BBPD also incorporates a hybrid control circuit to automate the frequency acquisition over a wide frequency range. Prototyped in a 28-nm CMOS, the proposed BBCDR occupies a tiny area of 0.0285 mm 2 and exhibits a 23-to-29-Gb/s capture range. The acquisition speed [8.2 Gb/s/<inline-formula> <tex-math notation="LaTeX">\mu \text{s} </tex-math></inline-formula>] and energy efficiency (0.68 pJ/bit) compare favorably with the state of the art.</description><identifier>ISSN: 0018-9200</identifier><identifier>EISSN: 1558-173X</identifier><identifier>DOI: 10.1109/JSSC.2021.3113773</identifier><identifier>CODEN: IJSCBC</identifier><language>eng</language><publisher>New York: IEEE</publisher><subject>Acquisition speed ; bang-bang clock and data recovery (BBCDR) ; charge pump (CP) ; Circuits ; Clock recovery ; Clocks ; CMOS ; Data recovery ; Detectors ; four-level pulse amplitude modulation (PAM-4) ; frequency detector (FD) ; Frequency modulation ; Frequency ranges ; Hybrid control ; hybrid control circuit (HCC) ; Jitter ; jitter tolerance (JTOL) ; jitter transfer function (JTF) ; Logic gates ; phase detector (PD) ; Phase detectors ; Pulse amplitude modulation ; strobe point (SP) ; Switches ; Voltage-controlled oscillators</subject><ispartof>IEEE journal of solid-state circuits, 2022-02, Vol.57 (2), p.546-561</ispartof><rights>Copyright The Institute of Electrical and Electronics Engineers, Inc. (IEEE) 2022</rights><lds50>peer_reviewed</lds50><woscitedreferencessubscribed>false</woscitedreferencessubscribed><orcidid>0000-0003-2821-648X ; 0000-0002-2794-1324 ; 0000-0002-3579-8740 ; 0000-0002-9447-8763</orcidid></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://ieeexplore.ieee.org/document/9552437$$EHTML$$P50$$Gieee$$H</linktohtml><link.rule.ids>314,780,784,796,27924,27925,54758</link.rule.ids><linktorsrc>$$Uhttps://ieeexplore.ieee.org/document/9552437$$EView_record_in_IEEE$$FView_record_in_$$GIEEE</linktorsrc></links><search><creatorcontrib>Zhao, Xiaoteng</creatorcontrib><creatorcontrib>Chen, Yong</creatorcontrib><creatorcontrib>Mak, Pui-In</creatorcontrib><creatorcontrib>Martins, Rui P.</creatorcontrib><title>A 0.0285-mm2 0.68-pJ/bit Single-Loop Full-Rate Bang-Bang CDR Without Reference and Separate FD Pulling Off an 8.2-Gb/s/μs Acquisition Speed of the PAM-4 Input in 28-nm CMOS</title><title>IEEE journal of solid-state circuits</title><addtitle>JSSC</addtitle><description>This article reports a single-loop full-rate bang-bang clock and data recovery (BBCDR) circuit supporting a four-level pulse amplitude modulation (PAM-4) pattern. We eliminate both the reference and the separate frequency detector (FD) by deliberately adding two fixed strobe points in the bang-bang phase detector (BBPD) curve via a clock-selection scheme. As such, we can achieve a wide frequency-capture range in a single-sided FD polarity. The BBPD also incorporates a hybrid control circuit to automate the frequency acquisition over a wide frequency range. Prototyped in a 28-nm CMOS, the proposed BBCDR occupies a tiny area of 0.0285 mm 2 and exhibits a 23-to-29-Gb/s capture range. The acquisition speed [8.2 Gb/s/<inline-formula> <tex-math notation="LaTeX">\mu \text{s} </tex-math></inline-formula>] and energy efficiency (0.68 pJ/bit) compare favorably with the state of the art.</description><subject>Acquisition speed</subject><subject>bang-bang clock and data recovery (BBCDR)</subject><subject>charge pump (CP)</subject><subject>Circuits</subject><subject>Clock recovery</subject><subject>Clocks</subject><subject>CMOS</subject><subject>Data recovery</subject><subject>Detectors</subject><subject>four-level pulse amplitude modulation (PAM-4)</subject><subject>frequency detector (FD)</subject><subject>Frequency modulation</subject><subject>Frequency ranges</subject><subject>Hybrid control</subject><subject>hybrid control circuit (HCC)</subject><subject>Jitter</subject><subject>jitter tolerance (JTOL)</subject><subject>jitter transfer function (JTF)</subject><subject>Logic gates</subject><subject>phase detector (PD)</subject><subject>Phase detectors</subject><subject>Pulse amplitude modulation</subject><subject>strobe point (SP)</subject><subject>Switches</subject><subject>Voltage-controlled oscillators</subject><issn>0018-9200</issn><issn>1558-173X</issn><fulltext>true</fulltext><rsrctype>article</rsrctype><creationdate>2022</creationdate><recordtype>article</recordtype><sourceid>RIE</sourceid><recordid>eNotkEtOwzAQhi0EEuVxAMRmJNZObcdJnGUJFFoVFTVIsKucZAyuWifNY8GhuAFn4Ey4gs08NP__jfQTcsVZwDlLx_M8zwLBBA9CzsMkCY_IiEeRojwJ347JiDGuaCoYOyVnXbfxq5SKj8jXBFjAhIrobif8GCvazMeF7SG37n2LdFHXDUyH7ZaudI9wq907PRTI7lbwavuPeuhhhQZbdCWCdhXk2Oj2IJ7ewbN3ehAsjfE3UIGgD8W4G_98dzAp94PtbG9rB3mDWEFtoP9AeJ48UQkz13i0dSAUdTvInpb5BTkxetvh5X8_Jy_T-5fskS6WD7NssqBWKkWLNOJKicpU0lSliGLGGCLXsjBlEhdJgXFoWFmmqkiFLlKmpI8s1Gl8MGISnpObP2zT1vsBu369qYfW-Y9rEYtQJoc0ver6T2URcd20dqfbz3UaRUJ62i9BPXRl</recordid><startdate>202202</startdate><enddate>202202</enddate><creator>Zhao, Xiaoteng</creator><creator>Chen, Yong</creator><creator>Mak, Pui-In</creator><creator>Martins, Rui P.</creator><general>IEEE</general><general>The Institute of Electrical and Electronics Engineers, Inc. (IEEE)</general><scope>97E</scope><scope>RIA</scope><scope>RIE</scope><scope>7SP</scope><scope>8FD</scope><scope>L7M</scope><orcidid>https://orcid.org/0000-0003-2821-648X</orcidid><orcidid>https://orcid.org/0000-0002-2794-1324</orcidid><orcidid>https://orcid.org/0000-0002-3579-8740</orcidid><orcidid>https://orcid.org/0000-0002-9447-8763</orcidid></search><sort><creationdate>202202</creationdate><title>A 0.0285-mm2 0.68-pJ/bit Single-Loop Full-Rate Bang-Bang CDR Without Reference and Separate FD Pulling Off an 8.2-Gb/s/μs Acquisition Speed of the PAM-4 Input in 28-nm CMOS</title><author>Zhao, Xiaoteng ; Chen, Yong ; Mak, Pui-In ; Martins, Rui P.</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-i488-b951882dfd4fdc256000ee1a4bfc76b7be63f0cc98b92ab90841373a969518e73</frbrgroupid><rsrctype>articles</rsrctype><prefilter>articles</prefilter><language>eng</language><creationdate>2022</creationdate><topic>Acquisition speed</topic><topic>bang-bang clock and data recovery (BBCDR)</topic><topic>charge pump (CP)</topic><topic>Circuits</topic><topic>Clock recovery</topic><topic>Clocks</topic><topic>CMOS</topic><topic>Data recovery</topic><topic>Detectors</topic><topic>four-level pulse amplitude modulation (PAM-4)</topic><topic>frequency detector (FD)</topic><topic>Frequency modulation</topic><topic>Frequency ranges</topic><topic>Hybrid control</topic><topic>hybrid control circuit (HCC)</topic><topic>Jitter</topic><topic>jitter tolerance (JTOL)</topic><topic>jitter transfer function (JTF)</topic><topic>Logic gates</topic><topic>phase detector (PD)</topic><topic>Phase detectors</topic><topic>Pulse amplitude modulation</topic><topic>strobe point (SP)</topic><topic>Switches</topic><topic>Voltage-controlled oscillators</topic><toplevel>peer_reviewed</toplevel><toplevel>online_resources</toplevel><creatorcontrib>Zhao, Xiaoteng</creatorcontrib><creatorcontrib>Chen, Yong</creatorcontrib><creatorcontrib>Mak, Pui-In</creatorcontrib><creatorcontrib>Martins, Rui P.</creatorcontrib><collection>IEEE All-Society Periodicals Package (ASPP) 2005-present</collection><collection>IEEE All-Society Periodicals Package (ASPP) 1998-Present</collection><collection>IEEE Electronic Library (IEL)</collection><collection>Electronics & Communications Abstracts</collection><collection>Technology Research Database</collection><collection>Advanced Technologies Database with Aerospace</collection><jtitle>IEEE journal of solid-state circuits</jtitle></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Zhao, Xiaoteng</au><au>Chen, Yong</au><au>Mak, Pui-In</au><au>Martins, Rui P.</au><format>journal</format><genre>article</genre><ristype>JOUR</ristype><atitle>A 0.0285-mm2 0.68-pJ/bit Single-Loop Full-Rate Bang-Bang CDR Without Reference and Separate FD Pulling Off an 8.2-Gb/s/μs Acquisition Speed of the PAM-4 Input in 28-nm CMOS</atitle><jtitle>IEEE journal of solid-state circuits</jtitle><stitle>JSSC</stitle><date>2022-02</date><risdate>2022</risdate><volume>57</volume><issue>2</issue><spage>546</spage><epage>561</epage><pages>546-561</pages><issn>0018-9200</issn><eissn>1558-173X</eissn><coden>IJSCBC</coden><abstract>This article reports a single-loop full-rate bang-bang clock and data recovery (BBCDR) circuit supporting a four-level pulse amplitude modulation (PAM-4) pattern. We eliminate both the reference and the separate frequency detector (FD) by deliberately adding two fixed strobe points in the bang-bang phase detector (BBPD) curve via a clock-selection scheme. As such, we can achieve a wide frequency-capture range in a single-sided FD polarity. The BBPD also incorporates a hybrid control circuit to automate the frequency acquisition over a wide frequency range. Prototyped in a 28-nm CMOS, the proposed BBCDR occupies a tiny area of 0.0285 mm 2 and exhibits a 23-to-29-Gb/s capture range. The acquisition speed [8.2 Gb/s/<inline-formula> <tex-math notation="LaTeX">\mu \text{s} </tex-math></inline-formula>] and energy efficiency (0.68 pJ/bit) compare favorably with the state of the art.</abstract><cop>New York</cop><pub>IEEE</pub><doi>10.1109/JSSC.2021.3113773</doi><tpages>16</tpages><orcidid>https://orcid.org/0000-0003-2821-648X</orcidid><orcidid>https://orcid.org/0000-0002-2794-1324</orcidid><orcidid>https://orcid.org/0000-0002-3579-8740</orcidid><orcidid>https://orcid.org/0000-0002-9447-8763</orcidid></addata></record> |
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| language | eng |
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| source | IEEE Electronic Library (IEL) |
| subjects | Acquisition speed bang-bang clock and data recovery (BBCDR) charge pump (CP) Circuits Clock recovery Clocks CMOS Data recovery Detectors four-level pulse amplitude modulation (PAM-4) frequency detector (FD) Frequency modulation Frequency ranges Hybrid control hybrid control circuit (HCC) Jitter jitter tolerance (JTOL) jitter transfer function (JTF) Logic gates phase detector (PD) Phase detectors Pulse amplitude modulation strobe point (SP) Switches Voltage-controlled oscillators |
| title | A 0.0285-mm2 0.68-pJ/bit Single-Loop Full-Rate Bang-Bang CDR Without Reference and Separate FD Pulling Off an 8.2-Gb/s/μs Acquisition Speed of the PAM-4 Input in 28-nm CMOS |
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