Area and system clock effects on SMT/CMP processors
Two approaches to high throughput processors are chip multiprocessing (CMP) and simultaneous multi-threading (SMT). CMP increases layout efficiency, which allows more functional units and a faster clock rate. However, CMP suffers from hardware partitioning of functional resources. SMT increases func...
Gespeichert in:
| Hauptverfasser: | , |
|---|---|
| Format: | Tagungsbericht |
| Sprache: | eng |
| Schlagworte: | |
| Online-Zugang: | Volltext bestellen |
| Tags: |
Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
|
| container_end_page | 218 |
|---|---|
| container_issue | |
| container_start_page | 211 |
| container_title | |
| container_volume | |
| creator | Burns, J. Gaudiot, J.-L. |
| description | Two approaches to high throughput processors are chip multiprocessing (CMP) and simultaneous multi-threading (SMT). CMP increases layout efficiency, which allows more functional units and a faster clock rate. However, CMP suffers from hardware partitioning of functional resources. SMT increases functional unit utilization by issuing instructions simultaneously from multiple threads. However, a wide-issue SMT suffers from layout and technology implementation problems. We use silicon resources as our basis for comparison and find that area and system clock have a large effect on the optimal SMT/CCMP design trade. We show the area overhead of SMT on each processor and how it scales with the width of the processor pipeline and the number of SMT threads. The wide issue SMT delivers the highest single-thread performance with improved multi-thread throughput. However multiple smaller cores deliver the highest throughput. |
| doi_str_mv | 10.1109/PACT.2001.953301 |
| format | Conference Proceeding |
| fullrecord | <record><control><sourceid>ieee_6IE</sourceid><recordid>TN_cdi_ieee_primary_953301</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><ieee_id>953301</ieee_id><sourcerecordid>953301</sourcerecordid><originalsourceid>FETCH-LOGICAL-i146t-bad1074ed150295fcd934941ce5d3139b745959a7dc24885e5eaffebb8b73e2e3</originalsourceid><addsrcrecordid>eNotj8tqwzAQRQVtoWmafelKP2BnxiNZnqUxfUFCA3WhuyDLY3CbxMHyJn_fQHI3Z3cOV6knhBQReLkpqzrNADBlSwR4ox7A5WyRcipu1Qyh4MRx_nOvFjH-wnnEOYCZKSpH8dofWh1PcZK9Drsh_GnpOglT1MNBf63rZbXe6OM4BIlxGOOjuuv8Lsriyrn6fn2pq_dk9fn2UZWrpEeTT0njWwRnpEULGdsutEyGDQaxLSFx44xly961ITNFYcWKP2ebpmgcSSY0V88Xby8i2-PY7_142l4u0j-eM0PQ</addsrcrecordid><sourcetype>Publisher</sourcetype><iscdi>true</iscdi><recordtype>conference_proceeding</recordtype></control><display><type>conference_proceeding</type><title>Area and system clock effects on SMT/CMP processors</title><source>IEEE Electronic Library (IEL) Conference Proceedings</source><creator>Burns, J. ; Gaudiot, J.-L.</creator><creatorcontrib>Burns, J. ; Gaudiot, J.-L.</creatorcontrib><description>Two approaches to high throughput processors are chip multiprocessing (CMP) and simultaneous multi-threading (SMT). CMP increases layout efficiency, which allows more functional units and a faster clock rate. However, CMP suffers from hardware partitioning of functional resources. SMT increases functional unit utilization by issuing instructions simultaneously from multiple threads. However, a wide-issue SMT suffers from layout and technology implementation problems. We use silicon resources as our basis for comparison and find that area and system clock have a large effect on the optimal SMT/CCMP design trade. We show the area overhead of SMT on each processor and how it scales with the width of the processor pipeline and the number of SMT threads. The wide issue SMT delivers the highest single-thread performance with improved multi-thread throughput. However multiple smaller cores deliver the highest throughput.</description><identifier>ISSN: 1089-796X</identifier><identifier>ISBN: 0769513638</identifier><identifier>ISBN: 9780769513638</identifier><identifier>DOI: 10.1109/PACT.2001.953301</identifier><language>eng</language><publisher>IEEE</publisher><subject>Clocks ; Delay estimation ; Hardware ; Microarchitecture ; Pipelines ; Routing ; Silicon ; Surface-mount technology ; Throughput ; Yarn</subject><ispartof>Proceedings 2001 International Conference on Parallel Architectures and Compilation Techniques, 2001, p.211-218</ispartof><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://ieeexplore.ieee.org/document/953301$$EHTML$$P50$$Gieee$$H</linktohtml><link.rule.ids>309,310,780,784,789,790,2058,4050,4051,27925,54920</link.rule.ids><linktorsrc>$$Uhttps://ieeexplore.ieee.org/document/953301$$EView_record_in_IEEE$$FView_record_in_$$GIEEE</linktorsrc></links><search><creatorcontrib>Burns, J.</creatorcontrib><creatorcontrib>Gaudiot, J.-L.</creatorcontrib><title>Area and system clock effects on SMT/CMP processors</title><title>Proceedings 2001 International Conference on Parallel Architectures and Compilation Techniques</title><addtitle>PACT</addtitle><description>Two approaches to high throughput processors are chip multiprocessing (CMP) and simultaneous multi-threading (SMT). CMP increases layout efficiency, which allows more functional units and a faster clock rate. However, CMP suffers from hardware partitioning of functional resources. SMT increases functional unit utilization by issuing instructions simultaneously from multiple threads. However, a wide-issue SMT suffers from layout and technology implementation problems. We use silicon resources as our basis for comparison and find that area and system clock have a large effect on the optimal SMT/CCMP design trade. We show the area overhead of SMT on each processor and how it scales with the width of the processor pipeline and the number of SMT threads. The wide issue SMT delivers the highest single-thread performance with improved multi-thread throughput. However multiple smaller cores deliver the highest throughput.</description><subject>Clocks</subject><subject>Delay estimation</subject><subject>Hardware</subject><subject>Microarchitecture</subject><subject>Pipelines</subject><subject>Routing</subject><subject>Silicon</subject><subject>Surface-mount technology</subject><subject>Throughput</subject><subject>Yarn</subject><issn>1089-796X</issn><isbn>0769513638</isbn><isbn>9780769513638</isbn><fulltext>true</fulltext><rsrctype>conference_proceeding</rsrctype><creationdate>2001</creationdate><recordtype>conference_proceeding</recordtype><sourceid>6IE</sourceid><sourceid>RIE</sourceid><recordid>eNotj8tqwzAQRQVtoWmafelKP2BnxiNZnqUxfUFCA3WhuyDLY3CbxMHyJn_fQHI3Z3cOV6knhBQReLkpqzrNADBlSwR4ox7A5WyRcipu1Qyh4MRx_nOvFjH-wnnEOYCZKSpH8dofWh1PcZK9Drsh_GnpOglT1MNBf63rZbXe6OM4BIlxGOOjuuv8Lsriyrn6fn2pq_dk9fn2UZWrpEeTT0njWwRnpEULGdsutEyGDQaxLSFx44xly961ITNFYcWKP2ebpmgcSSY0V88Xby8i2-PY7_142l4u0j-eM0PQ</recordid><startdate>2001</startdate><enddate>2001</enddate><creator>Burns, J.</creator><creator>Gaudiot, J.-L.</creator><general>IEEE</general><scope>6IE</scope><scope>6IL</scope><scope>CBEJK</scope><scope>RIE</scope><scope>RIL</scope></search><sort><creationdate>2001</creationdate><title>Area and system clock effects on SMT/CMP processors</title><author>Burns, J. ; Gaudiot, J.-L.</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-i146t-bad1074ed150295fcd934941ce5d3139b745959a7dc24885e5eaffebb8b73e2e3</frbrgroupid><rsrctype>conference_proceedings</rsrctype><prefilter>conference_proceedings</prefilter><language>eng</language><creationdate>2001</creationdate><topic>Clocks</topic><topic>Delay estimation</topic><topic>Hardware</topic><topic>Microarchitecture</topic><topic>Pipelines</topic><topic>Routing</topic><topic>Silicon</topic><topic>Surface-mount technology</topic><topic>Throughput</topic><topic>Yarn</topic><toplevel>online_resources</toplevel><creatorcontrib>Burns, J.</creatorcontrib><creatorcontrib>Gaudiot, J.-L.</creatorcontrib><collection>IEEE Electronic Library (IEL) Conference Proceedings</collection><collection>IEEE Proceedings Order Plan All Online (POP All Online) 1998-present by volume</collection><collection>IEEE Xplore All Conference Proceedings</collection><collection>IEEE Electronic Library (IEL)</collection><collection>IEEE Proceedings Order Plans (POP All) 1998-Present</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Burns, J.</au><au>Gaudiot, J.-L.</au><format>book</format><genre>proceeding</genre><ristype>CONF</ristype><atitle>Area and system clock effects on SMT/CMP processors</atitle><btitle>Proceedings 2001 International Conference on Parallel Architectures and Compilation Techniques</btitle><stitle>PACT</stitle><date>2001</date><risdate>2001</risdate><spage>211</spage><epage>218</epage><pages>211-218</pages><issn>1089-796X</issn><isbn>0769513638</isbn><isbn>9780769513638</isbn><abstract>Two approaches to high throughput processors are chip multiprocessing (CMP) and simultaneous multi-threading (SMT). CMP increases layout efficiency, which allows more functional units and a faster clock rate. However, CMP suffers from hardware partitioning of functional resources. SMT increases functional unit utilization by issuing instructions simultaneously from multiple threads. However, a wide-issue SMT suffers from layout and technology implementation problems. We use silicon resources as our basis for comparison and find that area and system clock have a large effect on the optimal SMT/CCMP design trade. We show the area overhead of SMT on each processor and how it scales with the width of the processor pipeline and the number of SMT threads. The wide issue SMT delivers the highest single-thread performance with improved multi-thread throughput. However multiple smaller cores deliver the highest throughput.</abstract><pub>IEEE</pub><doi>10.1109/PACT.2001.953301</doi><tpages>8</tpages><oa>free_for_read</oa></addata></record> |
| fulltext | fulltext_linktorsrc |
| identifier | ISSN: 1089-796X |
| ispartof | Proceedings 2001 International Conference on Parallel Architectures and Compilation Techniques, 2001, p.211-218 |
| issn | 1089-796X |
| language | eng |
| recordid | cdi_ieee_primary_953301 |
| source | IEEE Electronic Library (IEL) Conference Proceedings |
| subjects | Clocks Delay estimation Hardware Microarchitecture Pipelines Routing Silicon Surface-mount technology Throughput Yarn |
| title | Area and system clock effects on SMT/CMP processors |
| url | https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-01-06T08%3A58%3A09IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-ieee_6IE&rft_val_fmt=info:ofi/fmt:kev:mtx:book&rft.genre=proceeding&rft.atitle=Area%20and%20system%20clock%20effects%20on%20SMT/CMP%20processors&rft.btitle=Proceedings%202001%20International%20Conference%20on%20Parallel%20Architectures%20and%20Compilation%20Techniques&rft.au=Burns,%20J.&rft.date=2001&rft.spage=211&rft.epage=218&rft.pages=211-218&rft.issn=1089-796X&rft.isbn=0769513638&rft.isbn_list=9780769513638&rft_id=info:doi/10.1109/PACT.2001.953301&rft_dat=%3Cieee_6IE%3E953301%3C/ieee_6IE%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rft_ieee_id=953301&rfr_iscdi=true |