A low-power cache system for embedded processors
A low-power cache structure for embedded processors, called a cooperative cache system, is presented in this paper. The cooperative cache system reduces power consumption of the cache system by virtue of the structural characteristics that consists of two separate caches having different associativi...
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| container_end_page | 319 vol.1 |
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| creator | Gi-Ho Park Kil-Whan Lee Jang-Soo Lee Tack-Don Han Shin-Dug Kim Yong-Chun Kim Seh-Woong Jeong Kwang-Yup Lee |
| description | A low-power cache structure for embedded processors, called a cooperative cache system, is presented in this paper. The cooperative cache system reduces power consumption of the cache system by virtue of the structural characteristics that consists of two separate caches having different associativities and block sizes. The cooperative cache system is adopted as the cache structure for the CalmRISC-32 embedded processor, the prototype chip of which was recently manufactured with a 0.25 /spl mu/m, 4-metal process by Samsung Electronics Co. |
| doi_str_mv | 10.1109/MWSCAS.2000.951650 |
| format | Conference Proceeding |
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| identifier | ISBN: 9780780364752 |
| ispartof | Proceedings of the 43rd IEEE Midwest Symposium on Circuits and Systems (Cat.No.CH37144), 2000, Vol.1, p.316-319 vol.1 |
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| language | eng |
| recordid | cdi_ieee_primary_951650 |
| source | IEEE Electronic Library (IEL) Conference Proceedings |
| subjects | Application specific integrated circuits Computer science Cooperative caching Design engineering Embedded computing Energy consumption Large scale integration Manufacturing processes Power engineering and energy Power engineering computing |
| title | A low-power cache system for embedded processors |
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