A parallel approach for testing multi-port static random access memories
This paper presents a novel approach for testing multiport memories. This approach is based on the parallel execution of the testing process so that inter-port faults (shorts and coupling faults) can be detected at no loss of coverage and with no increase in the number of tests compared with a singl...
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| creator | Karimi, F. Irrinki, S. Crosbuy, T. Lombardi, F. |
| description | This paper presents a novel approach for testing multiport memories. This approach is based on the parallel execution of the testing process so that inter-port faults (shorts and coupling faults) can be detected at no loss of coverage and with no increase in the number of tests compared with a single-port memory. The parallelization is based on partitioning the memory into so-called segments. Test is completed in several phases. In each phase, the operation of a port is restricted to a segment. A port assignment process is utilized together with the partitioning of the memory; it considers the functionalities of the ports and their relation with respect to the addresses and the placement of the cells. |
| doi_str_mv | 10.1109/MTDT.2001.945233 |
| format | Conference Proceeding |
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This approach is based on the parallel execution of the testing process so that inter-port faults (shorts and coupling faults) can be detected at no loss of coverage and with no increase in the number of tests compared with a single-port memory. The parallelization is based on partitioning the memory into so-called segments. Test is completed in several phases. In each phase, the operation of a port is restricted to a segment. A port assignment process is utilized together with the partitioning of the memory; it considers the functionalities of the ports and their relation with respect to the addresses and the placement of the cells.</description><identifier>ISBN: 0769512429</identifier><identifier>ISBN: 9780769512426</identifier><identifier>DOI: 10.1109/MTDT.2001.945233</identifier><language>eng</language><publisher>IEEE</publisher><subject>Communication switching ; Fault detection ; Logic ; Manufacturing processes ; Microprocessors ; Read-write memory ; Switches ; System testing ; System-on-a-chip ; Wide area networks</subject><ispartof>Proceedings 2001 IEEE International Workshop on Memory Technology, Design and Testing, 2001, p.73-81</ispartof><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://ieeexplore.ieee.org/document/945233$$EHTML$$P50$$Gieee$$H</linktohtml><link.rule.ids>309,310,776,780,785,786,2051,4035,4036,27904,54899</link.rule.ids><linktorsrc>$$Uhttps://ieeexplore.ieee.org/document/945233$$EView_record_in_IEEE$$FView_record_in_$$GIEEE</linktorsrc></links><search><creatorcontrib>Karimi, F.</creatorcontrib><creatorcontrib>Irrinki, S.</creatorcontrib><creatorcontrib>Crosbuy, T.</creatorcontrib><creatorcontrib>Lombardi, F.</creatorcontrib><title>A parallel approach for testing multi-port static random access memories</title><title>Proceedings 2001 IEEE International Workshop on Memory Technology, Design and Testing</title><addtitle>MTDT</addtitle><description>This paper presents a novel approach for testing multiport memories. This approach is based on the parallel execution of the testing process so that inter-port faults (shorts and coupling faults) can be detected at no loss of coverage and with no increase in the number of tests compared with a single-port memory. The parallelization is based on partitioning the memory into so-called segments. Test is completed in several phases. In each phase, the operation of a port is restricted to a segment. A port assignment process is utilized together with the partitioning of the memory; it considers the functionalities of the ports and their relation with respect to the addresses and the placement of the cells.</description><subject>Communication switching</subject><subject>Fault detection</subject><subject>Logic</subject><subject>Manufacturing processes</subject><subject>Microprocessors</subject><subject>Read-write memory</subject><subject>Switches</subject><subject>System testing</subject><subject>System-on-a-chip</subject><subject>Wide area networks</subject><isbn>0769512429</isbn><isbn>9780769512426</isbn><fulltext>true</fulltext><rsrctype>conference_proceeding</rsrctype><creationdate>2001</creationdate><recordtype>conference_proceeding</recordtype><sourceid>6IE</sourceid><sourceid>RIE</sourceid><recordid>eNotjz1PwzAUAC0hJKB0R0z-Awl-TmzHY1U-WqmIJczVi_0MRkkT2Wbg34NUbrntpGPsDkQNIOzDa__Y11IIqG2rZNNcsBthtFUgW2mv2DrnL_GHEkZIec12G75gwnGkkeOypBndJw9z4oVyiacPPn2PJVbLnArPBUt0POHJzxNH5yhnPtE0p0j5ll0GHDOt_71i789P_XZXHd5e9tvNoYpgZKnAW49AtutUZyiANlqgV9Ra57wbsAPtBiCyAaDTbZAIgbQy0g1SDOibFbs_dyMRHZcUJ0w_x_Nr8wtp2kta</recordid><startdate>2001</startdate><enddate>2001</enddate><creator>Karimi, F.</creator><creator>Irrinki, S.</creator><creator>Crosbuy, T.</creator><creator>Lombardi, F.</creator><general>IEEE</general><scope>6IE</scope><scope>6IH</scope><scope>CBEJK</scope><scope>RIE</scope><scope>RIO</scope></search><sort><creationdate>2001</creationdate><title>A parallel approach for testing multi-port static random access memories</title><author>Karimi, F. ; Irrinki, S. ; Crosbuy, T. ; Lombardi, F.</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-i172t-1d9da1e988587ef16760ad5e49ccdcba816cb1ee9f11864f2a1fe6572cb20bad3</frbrgroupid><rsrctype>conference_proceedings</rsrctype><prefilter>conference_proceedings</prefilter><language>eng</language><creationdate>2001</creationdate><topic>Communication switching</topic><topic>Fault detection</topic><topic>Logic</topic><topic>Manufacturing processes</topic><topic>Microprocessors</topic><topic>Read-write memory</topic><topic>Switches</topic><topic>System testing</topic><topic>System-on-a-chip</topic><topic>Wide area networks</topic><toplevel>online_resources</toplevel><creatorcontrib>Karimi, F.</creatorcontrib><creatorcontrib>Irrinki, S.</creatorcontrib><creatorcontrib>Crosbuy, T.</creatorcontrib><creatorcontrib>Lombardi, F.</creatorcontrib><collection>IEEE Electronic Library (IEL) Conference Proceedings</collection><collection>IEEE Proceedings Order Plan (POP) 1998-present by volume</collection><collection>IEEE Xplore All Conference Proceedings</collection><collection>IEEE Electronic Library (IEL)</collection><collection>IEEE Proceedings Order Plans (POP) 1998-present</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Karimi, F.</au><au>Irrinki, S.</au><au>Crosbuy, T.</au><au>Lombardi, F.</au><format>book</format><genre>proceeding</genre><ristype>CONF</ristype><atitle>A parallel approach for testing multi-port static random access memories</atitle><btitle>Proceedings 2001 IEEE International Workshop on Memory Technology, Design and Testing</btitle><stitle>MTDT</stitle><date>2001</date><risdate>2001</risdate><spage>73</spage><epage>81</epage><pages>73-81</pages><isbn>0769512429</isbn><isbn>9780769512426</isbn><abstract>This paper presents a novel approach for testing multiport memories. This approach is based on the parallel execution of the testing process so that inter-port faults (shorts and coupling faults) can be detected at no loss of coverage and with no increase in the number of tests compared with a single-port memory. The parallelization is based on partitioning the memory into so-called segments. Test is completed in several phases. In each phase, the operation of a port is restricted to a segment. A port assignment process is utilized together with the partitioning of the memory; it considers the functionalities of the ports and their relation with respect to the addresses and the placement of the cells.</abstract><pub>IEEE</pub><doi>10.1109/MTDT.2001.945233</doi><tpages>9</tpages></addata></record> |
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| ispartof | Proceedings 2001 IEEE International Workshop on Memory Technology, Design and Testing, 2001, p.73-81 |
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| source | IEEE Electronic Library (IEL) Conference Proceedings |
| subjects | Communication switching Fault detection Logic Manufacturing processes Microprocessors Read-write memory Switches System testing System-on-a-chip Wide area networks |
| title | A parallel approach for testing multi-port static random access memories |
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