SPHERE: A Multi-SoC Architecture for Next-Generation Cyber-Physical Systems Based on Heterogeneous Platforms
This paper presents SPHERE, a project aimed at the realization of an integrated framework to abstract the hardware complexity of interconnected, modern system-on-chips (SoC) and simplify the management of their heterogeneous computational resources. The SPHERE framework leverages hypervisor technolo...
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creator | Biondi, Alessandro Casini, Daniel Cicero, Giorgiomaria Borgioli, Niccolo Buttazzo, Giorgio Patti, Gaetano Leonardi, Luca Bello, Lucia Lo Solieri, Marco Burgio, Paolo Olmedo, Ignacio Sanudo Ruocco, Angelo Palazzi, Luca Bertogna, Marko Cilardo, Alessandro Mazzocca, Nicola Mazzeo, Antonino |
description | This paper presents SPHERE, a project aimed at the realization of an integrated framework to abstract the hardware complexity of interconnected, modern system-on-chips (SoC) and simplify the management of their heterogeneous computational resources. The SPHERE framework leverages hypervisor technology to virtualize computational resources and isolate the behavior of different subsystems running on the same platform, while providing safety, security, and real-time communication mechanisms. The main challenges addressed by SPHERE are discussed in the paper along with a set of new technologies developed in the context of the project. They include isolation mechanisms for mixed-criticality applications, predictable I/O virtualization, the management of time-sensitive networks with heterogeneous traffic flows, and the management of field-programmable gate arrays (FPGA) to provide efficient implementations for cryptography modules, as well as hardware acceleration for deep neural networks. The SPHERE architecture is validated through an autonomous driving use-case. |
doi_str_mv | 10.1109/ACCESS.2021.3080842 |
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fullrecord | <record><control><sourceid>proquest_ieee_</sourceid><recordid>TN_cdi_ieee_primary_9432853</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><ieee_id>9432853</ieee_id><doaj_id>oai_doaj_org_article_9d75e74581dc412a8422c359e082125b</doaj_id><sourcerecordid>2532302674</sourcerecordid><originalsourceid>FETCH-LOGICAL-c408t-3bbb4308c8d98ab7baba0c9c563a5860d5453a56f3da63181d3c6309784aca3e3</originalsourceid><addsrcrecordid>eNpNkcFu1DAQhiMEElXpE_RiiXMW22MnDrclWrqVCqwInK2JM9tmlV0X25G6b49LqgpfPBrP_82M_6K4FnwlBG8-rdt203UryaVYATfcKPmmuJCiakrQUL39L35fXMV44PmYnNL1RTF1u-3m5-YzW7Nv85TGsvMtWwf3MCZyaQ7E9j6w7_SUyhs6UcA0-hNrzz2FcvdwjqPDiXXnmOgY2ReMNLD8vqVEwd9ngZ8j202YMuUYPxTv9jhFunq5L4vfXze_2m159-Pmtl3flU5xk0ro-17lTZwZGoN93WOP3DVOV4DaVHzQSueo2sOAFQgjBnAV8KY2Ch0CwWVxu3AHjwf7GMYjhrP1ONp_CR_uLYY0uolsM9SaaqUzxCkhMX-edKAb4kYKqfvM-riwHoP_M1NM9uDncMrjW6lBApdVrXIVLFUu-BgD7V-7Cm6fXbKLS_bZJfviUlZdL6qRiF4VjQJpNMBfzryMcA</addsrcrecordid><sourcetype>Open Website</sourcetype><iscdi>true</iscdi><recordtype>article</recordtype><pqid>2532302674</pqid></control><display><type>article</type><title>SPHERE: A Multi-SoC Architecture for Next-Generation Cyber-Physical Systems Based on Heterogeneous Platforms</title><source>IEEE Open Access Journals</source><source>DOAJ Directory of Open Access Journals</source><source>EZB-FREE-00999 freely available EZB journals</source><creator>Biondi, Alessandro ; Casini, Daniel ; Cicero, Giorgiomaria ; Borgioli, Niccolo ; Buttazzo, Giorgio ; Patti, Gaetano ; Leonardi, Luca ; Bello, Lucia Lo ; Solieri, Marco ; Burgio, Paolo ; Olmedo, Ignacio Sanudo ; Ruocco, Angelo ; Palazzi, Luca ; Bertogna, Marko ; Cilardo, Alessandro ; Mazzocca, Nicola ; Mazzeo, Antonino</creator><creatorcontrib>Biondi, Alessandro ; Casini, Daniel ; Cicero, Giorgiomaria ; Borgioli, Niccolo ; Buttazzo, Giorgio ; Patti, Gaetano ; Leonardi, Luca ; Bello, Lucia Lo ; Solieri, Marco ; Burgio, Paolo ; Olmedo, Ignacio Sanudo ; Ruocco, Angelo ; Palazzi, Luca ; Bertogna, Marko ; Cilardo, Alessandro ; Mazzocca, Nicola ; Mazzeo, Antonino</creatorcontrib><description>This paper presents SPHERE, a project aimed at the realization of an integrated framework to abstract the hardware complexity of interconnected, modern system-on-chips (SoC) and simplify the management of their heterogeneous computational resources. The SPHERE framework leverages hypervisor technology to virtualize computational resources and isolate the behavior of different subsystems running on the same platform, while providing safety, security, and real-time communication mechanisms. The main challenges addressed by SPHERE are discussed in the paper along with a set of new technologies developed in the context of the project. They include isolation mechanisms for mixed-criticality applications, predictable I/O virtualization, the management of time-sensitive networks with heterogeneous traffic flows, and the management of field-programmable gate arrays (FPGA) to provide efficient implementations for cryptography modules, as well as hardware acceleration for deep neural networks. The SPHERE architecture is validated through an autonomous driving use-case.</description><identifier>ISSN: 2169-3536</identifier><identifier>EISSN: 2169-3536</identifier><identifier>DOI: 10.1109/ACCESS.2021.3080842</identifier><identifier>CODEN: IAECCG</identifier><language>eng</language><publisher>Piscataway: IEEE</publisher><subject>Artificial neural networks ; Computer architecture ; Cryptography ; Cyber-physical systems ; embedded systems ; Field programmable gate arrays ; FPGA ; Hardware ; hypervisor ; Linux ; New technology ; Real-time systems ; Resource management ; Safety ; Subsystems ; Switches ; Traffic management ; Virtual machine monitors ; Virtualization</subject><ispartof>IEEE access, 2021, Vol.9, p.75446-75459</ispartof><rights>Copyright The Institute of Electrical and Electronics Engineers, Inc. (IEEE) 2021</rights><lds50>peer_reviewed</lds50><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed><citedby>FETCH-LOGICAL-c408t-3bbb4308c8d98ab7baba0c9c563a5860d5453a56f3da63181d3c6309784aca3e3</citedby><cites>FETCH-LOGICAL-c408t-3bbb4308c8d98ab7baba0c9c563a5860d5453a56f3da63181d3c6309784aca3e3</cites><orcidid>0000-0001-7581-6862 ; 0000-0003-2115-4853 ; 0000-0003-4719-3631 ; 0000-0003-1954-7201 ; 0000-0002-0604-9783 ; 0000-0002-6625-9336 ; 0000-0003-3631-7504 ; 0000-0002-9709-5717</orcidid></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://ieeexplore.ieee.org/document/9432853$$EHTML$$P50$$Gieee$$Hfree_for_read</linktohtml><link.rule.ids>314,780,784,864,2102,4024,27633,27923,27924,27925,54933</link.rule.ids></links><search><creatorcontrib>Biondi, Alessandro</creatorcontrib><creatorcontrib>Casini, Daniel</creatorcontrib><creatorcontrib>Cicero, Giorgiomaria</creatorcontrib><creatorcontrib>Borgioli, Niccolo</creatorcontrib><creatorcontrib>Buttazzo, Giorgio</creatorcontrib><creatorcontrib>Patti, Gaetano</creatorcontrib><creatorcontrib>Leonardi, Luca</creatorcontrib><creatorcontrib>Bello, Lucia Lo</creatorcontrib><creatorcontrib>Solieri, Marco</creatorcontrib><creatorcontrib>Burgio, Paolo</creatorcontrib><creatorcontrib>Olmedo, Ignacio Sanudo</creatorcontrib><creatorcontrib>Ruocco, Angelo</creatorcontrib><creatorcontrib>Palazzi, Luca</creatorcontrib><creatorcontrib>Bertogna, Marko</creatorcontrib><creatorcontrib>Cilardo, Alessandro</creatorcontrib><creatorcontrib>Mazzocca, Nicola</creatorcontrib><creatorcontrib>Mazzeo, Antonino</creatorcontrib><title>SPHERE: A Multi-SoC Architecture for Next-Generation Cyber-Physical Systems Based on Heterogeneous Platforms</title><title>IEEE access</title><addtitle>Access</addtitle><description>This paper presents SPHERE, a project aimed at the realization of an integrated framework to abstract the hardware complexity of interconnected, modern system-on-chips (SoC) and simplify the management of their heterogeneous computational resources. The SPHERE framework leverages hypervisor technology to virtualize computational resources and isolate the behavior of different subsystems running on the same platform, while providing safety, security, and real-time communication mechanisms. The main challenges addressed by SPHERE are discussed in the paper along with a set of new technologies developed in the context of the project. They include isolation mechanisms for mixed-criticality applications, predictable I/O virtualization, the management of time-sensitive networks with heterogeneous traffic flows, and the management of field-programmable gate arrays (FPGA) to provide efficient implementations for cryptography modules, as well as hardware acceleration for deep neural networks. The SPHERE architecture is validated through an autonomous driving use-case.</description><subject>Artificial neural networks</subject><subject>Computer architecture</subject><subject>Cryptography</subject><subject>Cyber-physical systems</subject><subject>embedded systems</subject><subject>Field programmable gate arrays</subject><subject>FPGA</subject><subject>Hardware</subject><subject>hypervisor</subject><subject>Linux</subject><subject>New technology</subject><subject>Real-time systems</subject><subject>Resource management</subject><subject>Safety</subject><subject>Subsystems</subject><subject>Switches</subject><subject>Traffic management</subject><subject>Virtual machine monitors</subject><subject>Virtualization</subject><issn>2169-3536</issn><issn>2169-3536</issn><fulltext>true</fulltext><rsrctype>article</rsrctype><creationdate>2021</creationdate><recordtype>article</recordtype><sourceid>ESBDL</sourceid><sourceid>RIE</sourceid><sourceid>DOA</sourceid><recordid>eNpNkcFu1DAQhiMEElXpE_RiiXMW22MnDrclWrqVCqwInK2JM9tmlV0X25G6b49LqgpfPBrP_82M_6K4FnwlBG8-rdt203UryaVYATfcKPmmuJCiakrQUL39L35fXMV44PmYnNL1RTF1u-3m5-YzW7Nv85TGsvMtWwf3MCZyaQ7E9j6w7_SUyhs6UcA0-hNrzz2FcvdwjqPDiXXnmOgY2ReMNLD8vqVEwd9ngZ8j202YMuUYPxTv9jhFunq5L4vfXze_2m159-Pmtl3flU5xk0ro-17lTZwZGoN93WOP3DVOV4DaVHzQSueo2sOAFQgjBnAV8KY2Ch0CwWVxu3AHjwf7GMYjhrP1ONp_CR_uLYY0uolsM9SaaqUzxCkhMX-edKAb4kYKqfvM-riwHoP_M1NM9uDncMrjW6lBApdVrXIVLFUu-BgD7V-7Cm6fXbKLS_bZJfviUlZdL6qRiF4VjQJpNMBfzryMcA</recordid><startdate>2021</startdate><enddate>2021</enddate><creator>Biondi, Alessandro</creator><creator>Casini, Daniel</creator><creator>Cicero, Giorgiomaria</creator><creator>Borgioli, Niccolo</creator><creator>Buttazzo, Giorgio</creator><creator>Patti, Gaetano</creator><creator>Leonardi, Luca</creator><creator>Bello, Lucia Lo</creator><creator>Solieri, Marco</creator><creator>Burgio, Paolo</creator><creator>Olmedo, Ignacio Sanudo</creator><creator>Ruocco, Angelo</creator><creator>Palazzi, Luca</creator><creator>Bertogna, Marko</creator><creator>Cilardo, Alessandro</creator><creator>Mazzocca, Nicola</creator><creator>Mazzeo, Antonino</creator><general>IEEE</general><general>The Institute of Electrical and Electronics Engineers, Inc. (IEEE)</general><scope>97E</scope><scope>ESBDL</scope><scope>RIA</scope><scope>RIE</scope><scope>AAYXX</scope><scope>CITATION</scope><scope>7SC</scope><scope>7SP</scope><scope>7SR</scope><scope>8BQ</scope><scope>8FD</scope><scope>JG9</scope><scope>JQ2</scope><scope>L7M</scope><scope>L~C</scope><scope>L~D</scope><scope>DOA</scope><orcidid>https://orcid.org/0000-0001-7581-6862</orcidid><orcidid>https://orcid.org/0000-0003-2115-4853</orcidid><orcidid>https://orcid.org/0000-0003-4719-3631</orcidid><orcidid>https://orcid.org/0000-0003-1954-7201</orcidid><orcidid>https://orcid.org/0000-0002-0604-9783</orcidid><orcidid>https://orcid.org/0000-0002-6625-9336</orcidid><orcidid>https://orcid.org/0000-0003-3631-7504</orcidid><orcidid>https://orcid.org/0000-0002-9709-5717</orcidid></search><sort><creationdate>2021</creationdate><title>SPHERE: A Multi-SoC Architecture for Next-Generation Cyber-Physical Systems Based on Heterogeneous Platforms</title><author>Biondi, Alessandro ; Casini, Daniel ; Cicero, Giorgiomaria ; Borgioli, Niccolo ; Buttazzo, Giorgio ; Patti, Gaetano ; Leonardi, Luca ; Bello, Lucia Lo ; Solieri, Marco ; Burgio, Paolo ; Olmedo, Ignacio Sanudo ; Ruocco, Angelo ; Palazzi, Luca ; Bertogna, Marko ; Cilardo, Alessandro ; Mazzocca, Nicola ; Mazzeo, Antonino</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-c408t-3bbb4308c8d98ab7baba0c9c563a5860d5453a56f3da63181d3c6309784aca3e3</frbrgroupid><rsrctype>articles</rsrctype><prefilter>articles</prefilter><language>eng</language><creationdate>2021</creationdate><topic>Artificial neural networks</topic><topic>Computer architecture</topic><topic>Cryptography</topic><topic>Cyber-physical systems</topic><topic>embedded systems</topic><topic>Field programmable gate arrays</topic><topic>FPGA</topic><topic>Hardware</topic><topic>hypervisor</topic><topic>Linux</topic><topic>New technology</topic><topic>Real-time systems</topic><topic>Resource management</topic><topic>Safety</topic><topic>Subsystems</topic><topic>Switches</topic><topic>Traffic management</topic><topic>Virtual machine monitors</topic><topic>Virtualization</topic><toplevel>peer_reviewed</toplevel><toplevel>online_resources</toplevel><creatorcontrib>Biondi, Alessandro</creatorcontrib><creatorcontrib>Casini, Daniel</creatorcontrib><creatorcontrib>Cicero, Giorgiomaria</creatorcontrib><creatorcontrib>Borgioli, Niccolo</creatorcontrib><creatorcontrib>Buttazzo, Giorgio</creatorcontrib><creatorcontrib>Patti, Gaetano</creatorcontrib><creatorcontrib>Leonardi, Luca</creatorcontrib><creatorcontrib>Bello, Lucia Lo</creatorcontrib><creatorcontrib>Solieri, Marco</creatorcontrib><creatorcontrib>Burgio, Paolo</creatorcontrib><creatorcontrib>Olmedo, Ignacio Sanudo</creatorcontrib><creatorcontrib>Ruocco, Angelo</creatorcontrib><creatorcontrib>Palazzi, Luca</creatorcontrib><creatorcontrib>Bertogna, Marko</creatorcontrib><creatorcontrib>Cilardo, Alessandro</creatorcontrib><creatorcontrib>Mazzocca, Nicola</creatorcontrib><creatorcontrib>Mazzeo, Antonino</creatorcontrib><collection>IEEE All-Society Periodicals Package (ASPP) 2005-present</collection><collection>IEEE Open Access Journals</collection><collection>IEEE All-Society Periodicals Package (ASPP) 1998-Present</collection><collection>IEEE Electronic Library (IEL)</collection><collection>CrossRef</collection><collection>Computer and Information Systems Abstracts</collection><collection>Electronics & Communications Abstracts</collection><collection>Engineered Materials Abstracts</collection><collection>METADEX</collection><collection>Technology Research Database</collection><collection>Materials Research Database</collection><collection>ProQuest Computer Science Collection</collection><collection>Advanced Technologies Database with Aerospace</collection><collection>Computer and Information Systems Abstracts Academic</collection><collection>Computer and Information Systems Abstracts Professional</collection><collection>DOAJ Directory of Open Access Journals</collection><jtitle>IEEE access</jtitle></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext</fulltext></delivery><addata><au>Biondi, Alessandro</au><au>Casini, Daniel</au><au>Cicero, Giorgiomaria</au><au>Borgioli, Niccolo</au><au>Buttazzo, Giorgio</au><au>Patti, Gaetano</au><au>Leonardi, Luca</au><au>Bello, Lucia Lo</au><au>Solieri, Marco</au><au>Burgio, Paolo</au><au>Olmedo, Ignacio Sanudo</au><au>Ruocco, Angelo</au><au>Palazzi, Luca</au><au>Bertogna, Marko</au><au>Cilardo, Alessandro</au><au>Mazzocca, Nicola</au><au>Mazzeo, Antonino</au><format>journal</format><genre>article</genre><ristype>JOUR</ristype><atitle>SPHERE: A Multi-SoC Architecture for Next-Generation Cyber-Physical Systems Based on Heterogeneous Platforms</atitle><jtitle>IEEE access</jtitle><stitle>Access</stitle><date>2021</date><risdate>2021</risdate><volume>9</volume><spage>75446</spage><epage>75459</epage><pages>75446-75459</pages><issn>2169-3536</issn><eissn>2169-3536</eissn><coden>IAECCG</coden><abstract>This paper presents SPHERE, a project aimed at the realization of an integrated framework to abstract the hardware complexity of interconnected, modern system-on-chips (SoC) and simplify the management of their heterogeneous computational resources. The SPHERE framework leverages hypervisor technology to virtualize computational resources and isolate the behavior of different subsystems running on the same platform, while providing safety, security, and real-time communication mechanisms. The main challenges addressed by SPHERE are discussed in the paper along with a set of new technologies developed in the context of the project. They include isolation mechanisms for mixed-criticality applications, predictable I/O virtualization, the management of time-sensitive networks with heterogeneous traffic flows, and the management of field-programmable gate arrays (FPGA) to provide efficient implementations for cryptography modules, as well as hardware acceleration for deep neural networks. The SPHERE architecture is validated through an autonomous driving use-case.</abstract><cop>Piscataway</cop><pub>IEEE</pub><doi>10.1109/ACCESS.2021.3080842</doi><tpages>14</tpages><orcidid>https://orcid.org/0000-0001-7581-6862</orcidid><orcidid>https://orcid.org/0000-0003-2115-4853</orcidid><orcidid>https://orcid.org/0000-0003-4719-3631</orcidid><orcidid>https://orcid.org/0000-0003-1954-7201</orcidid><orcidid>https://orcid.org/0000-0002-0604-9783</orcidid><orcidid>https://orcid.org/0000-0002-6625-9336</orcidid><orcidid>https://orcid.org/0000-0003-3631-7504</orcidid><orcidid>https://orcid.org/0000-0002-9709-5717</orcidid><oa>free_for_read</oa></addata></record> |
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subjects | Artificial neural networks Computer architecture Cryptography Cyber-physical systems embedded systems Field programmable gate arrays FPGA Hardware hypervisor Linux New technology Real-time systems Resource management Safety Subsystems Switches Traffic management Virtual machine monitors Virtualization |
title | SPHERE: A Multi-SoC Architecture for Next-Generation Cyber-Physical Systems Based on Heterogeneous Platforms |
url | https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-01-02T23%3A48%3A57IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-proquest_ieee_&rft_val_fmt=info:ofi/fmt:kev:mtx:journal&rft.genre=article&rft.atitle=SPHERE:%20A%20Multi-SoC%20Architecture%20for%20Next-Generation%20Cyber-Physical%20Systems%20Based%20on%20Heterogeneous%20Platforms&rft.jtitle=IEEE%20access&rft.au=Biondi,%20Alessandro&rft.date=2021&rft.volume=9&rft.spage=75446&rft.epage=75459&rft.pages=75446-75459&rft.issn=2169-3536&rft.eissn=2169-3536&rft.coden=IAECCG&rft_id=info:doi/10.1109/ACCESS.2021.3080842&rft_dat=%3Cproquest_ieee_%3E2532302674%3C/proquest_ieee_%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_pqid=2532302674&rft_id=info:pmid/&rft_ieee_id=9432853&rft_doaj_id=oai_doaj_org_article_9d75e74581dc412a8422c359e082125b&rfr_iscdi=true |