High resistance via induced by marginal barrier metal step coverage and F diffusion

In submicron multilevel metallization CMOS devices, high resistance vias and open via contacts are a common issue that can cause low yield and reliability problems (Islamraja et al., 1992). Via failure modes such as contaminated via, delaminated via and blown via contacts have been well documented (...

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Bibliographische Detailangaben

Hauptverfasser:	Dai, J.Y., Loh, S.K., Tee, S.F., Tay, C.L., Ansari, S., Er, E., Redkar, S.
Format:	Tagungsbericht
Sprache:	eng
Schlagworte:	Amorphous materials Chemical vapor deposition Circuit testing Contact resistance Electrical resistance measurement Failure analysis High temperature superconductors Pollution measurement Tin Transmission electron microscopy
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