Implementation of fixed DSP functions using the reduced coefficient multiplier
Distributed arithmetic (DA) has been successfully applied to the design of area efficient multipliers on FPGAs for DSP applications. Whilst DA is efficient in applications where the coefficients are fixed, there is little option for applications with a limited range of coefficient values. This paper...
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| creator | Turner, R.H. Courtney, T. Woods, R. |
| description | Distributed arithmetic (DA) has been successfully applied to the design of area efficient multipliers on FPGAs for DSP applications. Whilst DA is efficient in applications where the coefficients are fixed, there is little option for applications with a limited range of coefficient values. This paper describes a technique for developing area efficient multipliers for a range of DSP applications that fall into this category. This is accomplished by employing multiplexers at no extra cost to increase the functionality of existing fixed coefficient multipliers. The technique has been applied to a DCT FPGA implementation where an area decrease of up to 50% and a speed increase of 33% was achieved over the conventional route. |
| doi_str_mv | 10.1109/ICASSP.2001.941056 |
| format | Conference Proceeding |
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Whilst DA is efficient in applications where the coefficients are fixed, there is little option for applications with a limited range of coefficient values. This paper describes a technique for developing area efficient multipliers for a range of DSP applications that fall into this category. This is accomplished by employing multiplexers at no extra cost to increase the functionality of existing fixed coefficient multipliers. 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The technique has been applied to a DCT FPGA implementation where an area decrease of up to 50% and a speed increase of 33% was achieved over the conventional route.</description><subject>Arithmetic</subject><subject>Buildings</subject><subject>Circuits</subject><subject>Cost function</subject><subject>Design engineering</subject><subject>Digital signal processing</subject><subject>Discrete cosine transforms</subject><subject>Field programmable gate arrays</subject><subject>Multiplexing</subject><subject>Table lookup</subject><issn>1520-6149</issn><issn>2379-190X</issn><isbn>0780370414</isbn><isbn>9780780370418</isbn><fulltext>true</fulltext><rsrctype>conference_proceeding</rsrctype><creationdate>2001</creationdate><recordtype>conference_proceeding</recordtype><sourceid>6IE</sourceid><sourceid>RIE</sourceid><recordid>eNotUMtKw0AUHXyAafUHupofSLx3MpnJLKVqLRQtpAt3ZTK5oyNJGvIA_XsjdXXgvDgcxlYICSKY--36oSj2iQDAxEiETF2wSKTaxGjg_ZItQOeQapAor1iEmYBYoTQ3bDEMXwCQa5lH7HXbdDU11I52DKeWnzz34Zsq_ljsuZ9a98cOfBpC-8HHT-I9VZObdXci74MLc5I3Uz2Grg7U37Jrb-uB7v5xyQ7PT4f1S7x728yDd3HI9RjnVioqTY6uVGTQggZhLGYGhBPCGjKepLJQWTU70cuM0JciFSids-jTJVudawMRHbs-NLb_OZ5fSH8BXUtQfg</recordid><startdate>2001</startdate><enddate>2001</enddate><creator>Turner, R.H.</creator><creator>Courtney, T.</creator><creator>Woods, R.</creator><general>IEEE</general><scope>6IE</scope><scope>6IH</scope><scope>CBEJK</scope><scope>RIE</scope><scope>RIO</scope></search><sort><creationdate>2001</creationdate><title>Implementation of fixed DSP functions using the reduced coefficient multiplier</title><author>Turner, R.H. ; Courtney, T. ; Woods, R.</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-i87t-8a46eb981cb6e91a07029a15902c22a9e9fe46a0da6a461f45e1fb23214cca1f3</frbrgroupid><rsrctype>conference_proceedings</rsrctype><prefilter>conference_proceedings</prefilter><language>eng</language><creationdate>2001</creationdate><topic>Arithmetic</topic><topic>Buildings</topic><topic>Circuits</topic><topic>Cost function</topic><topic>Design engineering</topic><topic>Digital signal processing</topic><topic>Discrete cosine transforms</topic><topic>Field programmable gate arrays</topic><topic>Multiplexing</topic><topic>Table lookup</topic><toplevel>online_resources</toplevel><creatorcontrib>Turner, R.H.</creatorcontrib><creatorcontrib>Courtney, T.</creatorcontrib><creatorcontrib>Woods, R.</creatorcontrib><collection>IEEE Electronic Library (IEL) Conference Proceedings</collection><collection>IEEE Proceedings Order Plan (POP) 1998-present by volume</collection><collection>IEEE Xplore All Conference Proceedings</collection><collection>IEEE Electronic Library (IEL)</collection><collection>IEEE Proceedings Order Plans (POP) 1998-present</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Turner, R.H.</au><au>Courtney, T.</au><au>Woods, R.</au><format>book</format><genre>proceeding</genre><ristype>CONF</ristype><atitle>Implementation of fixed DSP functions using the reduced coefficient multiplier</atitle><btitle>2001 IEEE International Conference on Acoustics, Speech, and Signal Processing. Proceedings (Cat. No.01CH37221)</btitle><stitle>ICASSP</stitle><date>2001</date><risdate>2001</risdate><volume>2</volume><spage>881</spage><epage>884 vol.2</epage><pages>881-884 vol.2</pages><issn>1520-6149</issn><eissn>2379-190X</eissn><isbn>0780370414</isbn><isbn>9780780370418</isbn><abstract>Distributed arithmetic (DA) has been successfully applied to the design of area efficient multipliers on FPGAs for DSP applications. Whilst DA is efficient in applications where the coefficients are fixed, there is little option for applications with a limited range of coefficient values. This paper describes a technique for developing area efficient multipliers for a range of DSP applications that fall into this category. This is accomplished by employing multiplexers at no extra cost to increase the functionality of existing fixed coefficient multipliers. The technique has been applied to a DCT FPGA implementation where an area decrease of up to 50% and a speed increase of 33% was achieved over the conventional route.</abstract><pub>IEEE</pub><doi>10.1109/ICASSP.2001.941056</doi></addata></record> |
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| ispartof | 2001 IEEE International Conference on Acoustics, Speech, and Signal Processing. Proceedings (Cat. No.01CH37221), 2001, Vol.2, p.881-884 vol.2 |
| issn | 1520-6149 2379-190X |
| language | eng |
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| source | IEEE Electronic Library (IEL) Conference Proceedings |
| subjects | Arithmetic Buildings Circuits Cost function Design engineering Digital signal processing Discrete cosine transforms Field programmable gate arrays Multiplexing Table lookup |
| title | Implementation of fixed DSP functions using the reduced coefficient multiplier |
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