Split-level precharge differential logic: a new type of high-speed charge-recycling differential logic

In this paper, a new charge-recycling differential logic named split-level precharge differential logic (SPDL) is presented. It employs a new push-pull type output driver which is simple and separated from the NMOS logic tree. Therefore, it can improve energy efficiency, driving capability, and reliability compared with the previous differential logic structures which use cross-coupled inverters as the output driver. To verify the reliability and the applicability of the proposed SPDL in VLSI systems, an 8-bit full adder is fabricated in a 0.6-/spl mu/m CMOS technology. Experimental results show that the performance of the SPDL is about two times as good as that of the previous half-rail differential logic (HRDL) in terms of power-delay product. Moreover, the SPDL has stable operation under mismatch or parameter variation.