Exploring and exploiting wire-level pipelining in emerging technologies
Pipelining is a technique that has long since been considered fundamental by computer architects. However, the world of nanoelectronics is pushing the idea of pipelining to new and lower levels-particularly the device level. How this affects circuits and the relationship between their timing, archit...
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| creator | Niemier, M.T. Kogge, P.M. |
| description | Pipelining is a technique that has long since been considered fundamental by computer architects. However, the world of nanoelectronics is pushing the idea of pipelining to new and lower levels-particularly the device level. How this affects circuits and the relationship between their timing, architecture, and design will be studied in the context of an inherently self-latching nanotechnology termed quantum cellular automata (QCA). Results indicate that this nanotechnology offers the potential for "free" multi-threading and "processing-in-wire". All of this could be accomplished in a technology that could be almost three orders of magnitude denser than an equivalent design fabricated in a process at the end of the CMOS curve. |
| doi_str_mv | 10.1109/ISCA.2001.937445 |
| format | Conference Proceeding |
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However, the world of nanoelectronics is pushing the idea of pipelining to new and lower levels-particularly the device level. How this affects circuits and the relationship between their timing, architecture, and design will be studied in the context of an inherently self-latching nanotechnology termed quantum cellular automata (QCA). Results indicate that this nanotechnology offers the potential for "free" multi-threading and "processing-in-wire". All of this could be accomplished in a technology that could be almost three orders of magnitude denser than an equivalent design fabricated in a process at the end of the CMOS curve.</description><subject>Circuits</subject><subject>CMOS technology</subject><subject>Computer science</subject><subject>Josephson junctions</subject><subject>Logic functions</subject><subject>Nanoelectronics</subject><subject>Nanotechnology</subject><subject>Pipeline processing</subject><subject>Quantum cellular automata</subject><subject>Timing</subject><issn>1063-6897</issn><issn>2575-713X</issn><isbn>0769511627</isbn><isbn>9780769511627</isbn><fulltext>true</fulltext><rsrctype>conference_proceeding</rsrctype><creationdate>2001</creationdate><recordtype>conference_proceeding</recordtype><sourceid>6IE</sourceid><sourceid>RIE</sourceid><recordid>eNp9jssOgjAURG98JIK6N674AbAF29qlMb7WunBniF7xmlJIIT7-XomuXc2cmUwyACPOIs6Znmx3i3kUM8YjnajpVLTAi4USoeLJoQ0-U1ILzmWsOuBxJpNQzrTqgV9Vt89IayE9WC-fpSkc2SxI7TnAhqhu8EEOQ4N3NEFJJRqyTUo2wBxd1vgaT1dbmCIjrAbQvaSmwuFP-zBeLfeLTUiIeCwd5al7Hb8_k7_lGwOFPuc</recordid><startdate>2001</startdate><enddate>2001</enddate><creator>Niemier, M.T.</creator><creator>Kogge, P.M.</creator><general>IEEE</general><scope>6IE</scope><scope>6IH</scope><scope>CBEJK</scope><scope>RIE</scope><scope>RIO</scope></search><sort><creationdate>2001</creationdate><title>Exploring and exploiting wire-level pipelining in emerging technologies</title><author>Niemier, M.T. ; Kogge, P.M.</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-ieee_primary_9374453</frbrgroupid><rsrctype>conference_proceedings</rsrctype><prefilter>conference_proceedings</prefilter><language>eng</language><creationdate>2001</creationdate><topic>Circuits</topic><topic>CMOS technology</topic><topic>Computer science</topic><topic>Josephson junctions</topic><topic>Logic functions</topic><topic>Nanoelectronics</topic><topic>Nanotechnology</topic><topic>Pipeline processing</topic><topic>Quantum cellular automata</topic><topic>Timing</topic><toplevel>online_resources</toplevel><creatorcontrib>Niemier, M.T.</creatorcontrib><creatorcontrib>Kogge, P.M.</creatorcontrib><collection>IEEE Electronic Library (IEL) Conference Proceedings</collection><collection>IEEE Proceedings Order Plan (POP) 1998-present by volume</collection><collection>IEEE Xplore All Conference Proceedings</collection><collection>IEEE Electronic Library (IEL)</collection><collection>IEEE Proceedings Order Plans (POP) 1998-present</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Niemier, M.T.</au><au>Kogge, P.M.</au><format>book</format><genre>proceeding</genre><ristype>CONF</ristype><atitle>Exploring and exploiting wire-level pipelining in emerging technologies</atitle><btitle>Proceedings 28th Annual International Symposium on Computer Architecture</btitle><stitle>ISCA</stitle><date>2001</date><risdate>2001</risdate><spage>166</spage><epage>177</epage><pages>166-177</pages><issn>1063-6897</issn><eissn>2575-713X</eissn><isbn>0769511627</isbn><isbn>9780769511627</isbn><abstract>Pipelining is a technique that has long since been considered fundamental by computer architects. However, the world of nanoelectronics is pushing the idea of pipelining to new and lower levels-particularly the device level. How this affects circuits and the relationship between their timing, architecture, and design will be studied in the context of an inherently self-latching nanotechnology termed quantum cellular automata (QCA). Results indicate that this nanotechnology offers the potential for "free" multi-threading and "processing-in-wire". All of this could be accomplished in a technology that could be almost three orders of magnitude denser than an equivalent design fabricated in a process at the end of the CMOS curve.</abstract><pub>IEEE</pub><doi>10.1109/ISCA.2001.937445</doi></addata></record> |
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| identifier | ISSN: 1063-6897 |
| ispartof | Proceedings 28th Annual International Symposium on Computer Architecture, 2001, p.166-177 |
| issn | 1063-6897 2575-713X |
| language | eng |
| recordid | cdi_ieee_primary_937445 |
| source | IEEE Electronic Library (IEL) Conference Proceedings |
| subjects | Circuits CMOS technology Computer science Josephson junctions Logic functions Nanoelectronics Nanotechnology Pipeline processing Quantum cellular automata Timing |
| title | Exploring and exploiting wire-level pipelining in emerging technologies |
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