Full CMP integration of CVD TiN damascene sub-0.1-/spl mu/m metal gate devices for ULSI applications

Full chemical mechanical polishing (CMP) process integration of a W/TiN damascene metal gate has been optimized and is demonstrated to be compatible with ULSI circuit fabrication. Highly uniform and reliable electrical characteristics are achieved for widely ranged MOS pattern structures (from 0.1-/...

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Veröffentlicht in:	IEEE transactions on electron devices 2001-08, Vol.48 (8), p.1816-1821
Hauptverfasser:	Ducroquet, F., Achard, H., Coudert, F., Previtali, B., Lugand, J.-F., Ulmer, L., Farjot, T., Gobil, Y., Heitzmann, M., Tedesco, S., Nier, M.E., Deleonibus, S.
Format:	Artikel
Sprache:	eng
Schlagworte:	Integrated circuit metallization
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