Investigation of Gate-Length Scaling of Ferroelectric FET

In this article, the device scaling of FeFET down to 22 nm and its impacts on memory performance and reliability has been investigated in detail using experimentally calibrated data. Lateral nonuniformity along the channel in the polarization of the ferroelectric layer is observed, which is shown to...

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Veröffentlicht in:	IEEE transactions on electron devices 2021-03, Vol.68 (3), p.1364-1368
Hauptverfasser:	Jindal, Sourabh, Manhas, Sanjeev Kumar, Gautam, Satendra Kumar, Balatti, Simone, Kumar, Arvind, Pakala, Mahendra
Format:	Artikel
Sprache:	eng
Schlagworte:	Capacitors Depolarization field Design optimization Electric fields FeFET FeFETs ferroelectric Ferroelectric materials Ferroelectricity Hafnium oxide interfacial layer (IL) Iron Logic gates Nonuniformity Permittivity Polarization Reliability Scaling Silicon State (computer science)
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