An ASIC methodology for the design of DSP standard products
An approach that has been used successfully in the design of a family of high-performance digital signal processing (DSP) standard products is described. It offers the advantage of a short design cycle without sacrificing performance. The methodology relies on the availability of a well characterize...
Gespeichert in:
| 1. Verfasser: | |
|---|---|
| Format: | Tagungsbericht |
| Sprache: | eng |
| Schlagworte: | |
| Online-Zugang: | Volltext bestellen |
| Tags: |
Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
|
| container_end_page | 5/6 |
|---|---|
| container_issue | |
| container_start_page | 5/1 |
| container_title | |
| container_volume | |
| creator | Ang, P.H. |
| description | An approach that has been used successfully in the design of a family of high-performance digital signal processing (DSP) standard products is described. It offers the advantage of a short design cycle without sacrificing performance. The methodology relies on the availability of a well characterized standard-cell library, an accurate gate-level simulator, a behavioral simulator for architectural evaluations, and module generators for generic DSP operators such as multipliers and adders. The methodology has the flexibility to retarget the logic or structural description into a physical implementation that can be either array-based, cell-based, or full custom. Two design case studies of 20-MHz DSP standard product chips are described.< > |
| doi_str_mv | 10.1109/CMPEUR.1989.93470 |
| format | Conference Proceeding |
| fullrecord | <record><control><sourceid>ieee_6IE</sourceid><recordid>TN_cdi_ieee_primary_93470</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><ieee_id>93470</ieee_id><sourcerecordid>93470</sourcerecordid><originalsourceid>FETCH-LOGICAL-g135t-f90386595a71533dd6720f9b6dbe5590baa5382f0638e0dcc710ac5f4d36cd8b3</originalsourceid><addsrcrecordid>eNotj9FOwjAUQJsYExX5AN76A5u33LVr49MyUUgwEpFn0u22YwZW0s4H_l6jnpfzdpLD2ExALgSYh_p1s9i958JokxssSrhid6CFVsIUoG7YNKVP-EFKDWhu2WM18Gq7qvnJjYdA4Ri6C_ch8vHgOLnUdwMPnj9tNzyNdiAbiZ9joK92TPfs2ttjctN_T9juefFRL7P128uqrtZZJ1COmTeAWkkjbSkkIpEq5-BNo6hxUhporJWo5x4UagfUtqUA20pfEKqWdIMTNvvr9s65_Tn2Jxsv-987_AYe8USM</addsrcrecordid><sourcetype>Publisher</sourcetype><iscdi>true</iscdi><recordtype>conference_proceeding</recordtype></control><display><type>conference_proceeding</type><title>An ASIC methodology for the design of DSP standard products</title><source>IEEE Electronic Library (IEL) Conference Proceedings</source><creator>Ang, P.H.</creator><creatorcontrib>Ang, P.H.</creatorcontrib><description>An approach that has been used successfully in the design of a family of high-performance digital signal processing (DSP) standard products is described. It offers the advantage of a short design cycle without sacrificing performance. The methodology relies on the availability of a well characterized standard-cell library, an accurate gate-level simulator, a behavioral simulator for architectural evaluations, and module generators for generic DSP operators such as multipliers and adders. The methodology has the flexibility to retarget the logic or structural description into a physical implementation that can be either array-based, cell-based, or full custom. Two design case studies of 20-MHz DSP standard product chips are described.< ></description><identifier>ISBN: 0818619406</identifier><identifier>ISBN: 9780818619403</identifier><identifier>DOI: 10.1109/CMPEUR.1989.93470</identifier><language>eng</language><publisher>IEEE Comput. Soc. Press</publisher><subject>Adders ; Application specific integrated circuits ; Availability ; Design methodology ; Digital signal processing ; Large scale integration ; Logic arrays ; Nonlinear filters ; Signal design ; Signal processing</subject><ispartof>Proceedings. VLSI and Computer Peripherals. COMPEURO 89, 1989, p.5/1-5/6</ispartof><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://ieeexplore.ieee.org/document/93470$$EHTML$$P50$$Gieee$$H</linktohtml><link.rule.ids>309,310,776,780,785,786,2052,4036,4037,27902,54895</link.rule.ids><linktorsrc>$$Uhttps://ieeexplore.ieee.org/document/93470$$EView_record_in_IEEE$$FView_record_in_$$GIEEE</linktorsrc></links><search><creatorcontrib>Ang, P.H.</creatorcontrib><title>An ASIC methodology for the design of DSP standard products</title><title>Proceedings. VLSI and Computer Peripherals. COMPEURO 89</title><addtitle>CMPEUR</addtitle><description>An approach that has been used successfully in the design of a family of high-performance digital signal processing (DSP) standard products is described. It offers the advantage of a short design cycle without sacrificing performance. The methodology relies on the availability of a well characterized standard-cell library, an accurate gate-level simulator, a behavioral simulator for architectural evaluations, and module generators for generic DSP operators such as multipliers and adders. The methodology has the flexibility to retarget the logic or structural description into a physical implementation that can be either array-based, cell-based, or full custom. Two design case studies of 20-MHz DSP standard product chips are described.< ></description><subject>Adders</subject><subject>Application specific integrated circuits</subject><subject>Availability</subject><subject>Design methodology</subject><subject>Digital signal processing</subject><subject>Large scale integration</subject><subject>Logic arrays</subject><subject>Nonlinear filters</subject><subject>Signal design</subject><subject>Signal processing</subject><isbn>0818619406</isbn><isbn>9780818619403</isbn><fulltext>true</fulltext><rsrctype>conference_proceeding</rsrctype><creationdate>1989</creationdate><recordtype>conference_proceeding</recordtype><sourceid>6IE</sourceid><sourceid>RIE</sourceid><recordid>eNotj9FOwjAUQJsYExX5AN76A5u33LVr49MyUUgwEpFn0u22YwZW0s4H_l6jnpfzdpLD2ExALgSYh_p1s9i958JokxssSrhid6CFVsIUoG7YNKVP-EFKDWhu2WM18Gq7qvnJjYdA4Ri6C_ch8vHgOLnUdwMPnj9tNzyNdiAbiZ9joK92TPfs2ttjctN_T9juefFRL7P128uqrtZZJ1COmTeAWkkjbSkkIpEq5-BNo6hxUhporJWo5x4UagfUtqUA20pfEKqWdIMTNvvr9s65_Tn2Jxsv-987_AYe8USM</recordid><startdate>1989</startdate><enddate>1989</enddate><creator>Ang, P.H.</creator><general>IEEE Comput. Soc. Press</general><scope>6IE</scope><scope>6IL</scope><scope>CBEJK</scope><scope>RIE</scope><scope>RIL</scope></search><sort><creationdate>1989</creationdate><title>An ASIC methodology for the design of DSP standard products</title><author>Ang, P.H.</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-g135t-f90386595a71533dd6720f9b6dbe5590baa5382f0638e0dcc710ac5f4d36cd8b3</frbrgroupid><rsrctype>conference_proceedings</rsrctype><prefilter>conference_proceedings</prefilter><language>eng</language><creationdate>1989</creationdate><topic>Adders</topic><topic>Application specific integrated circuits</topic><topic>Availability</topic><topic>Design methodology</topic><topic>Digital signal processing</topic><topic>Large scale integration</topic><topic>Logic arrays</topic><topic>Nonlinear filters</topic><topic>Signal design</topic><topic>Signal processing</topic><toplevel>online_resources</toplevel><creatorcontrib>Ang, P.H.</creatorcontrib><collection>IEEE Electronic Library (IEL) Conference Proceedings</collection><collection>IEEE Proceedings Order Plan All Online (POP All Online) 1998-present by volume</collection><collection>IEEE Xplore All Conference Proceedings</collection><collection>IEEE Electronic Library (IEL)</collection><collection>IEEE Proceedings Order Plans (POP All) 1998-Present</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Ang, P.H.</au><format>book</format><genre>proceeding</genre><ristype>CONF</ristype><atitle>An ASIC methodology for the design of DSP standard products</atitle><btitle>Proceedings. VLSI and Computer Peripherals. COMPEURO 89</btitle><stitle>CMPEUR</stitle><date>1989</date><risdate>1989</risdate><spage>5/1</spage><epage>5/6</epage><pages>5/1-5/6</pages><isbn>0818619406</isbn><isbn>9780818619403</isbn><abstract>An approach that has been used successfully in the design of a family of high-performance digital signal processing (DSP) standard products is described. It offers the advantage of a short design cycle without sacrificing performance. The methodology relies on the availability of a well characterized standard-cell library, an accurate gate-level simulator, a behavioral simulator for architectural evaluations, and module generators for generic DSP operators such as multipliers and adders. The methodology has the flexibility to retarget the logic or structural description into a physical implementation that can be either array-based, cell-based, or full custom. Two design case studies of 20-MHz DSP standard product chips are described.< ></abstract><pub>IEEE Comput. Soc. Press</pub><doi>10.1109/CMPEUR.1989.93470</doi></addata></record> |
| fulltext | fulltext_linktorsrc |
| identifier | ISBN: 0818619406 |
| ispartof | Proceedings. VLSI and Computer Peripherals. COMPEURO 89, 1989, p.5/1-5/6 |
| issn | |
| language | eng |
| recordid | cdi_ieee_primary_93470 |
| source | IEEE Electronic Library (IEL) Conference Proceedings |
| subjects | Adders Application specific integrated circuits Availability Design methodology Digital signal processing Large scale integration Logic arrays Nonlinear filters Signal design Signal processing |
| title | An ASIC methodology for the design of DSP standard products |
| url | https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-02-01T20%3A56%3A14IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-ieee_6IE&rft_val_fmt=info:ofi/fmt:kev:mtx:book&rft.genre=proceeding&rft.atitle=An%20ASIC%20methodology%20for%20the%20design%20of%20DSP%20standard%20products&rft.btitle=Proceedings.%20VLSI%20and%20Computer%20Peripherals.%20COMPEURO%2089&rft.au=Ang,%20P.H.&rft.date=1989&rft.spage=5/1&rft.epage=5/6&rft.pages=5/1-5/6&rft.isbn=0818619406&rft.isbn_list=9780818619403&rft_id=info:doi/10.1109/CMPEUR.1989.93470&rft_dat=%3Cieee_6IE%3E93470%3C/ieee_6IE%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rft_ieee_id=93470&rfr_iscdi=true |