A High-Performance and Low-Cost Montgomery Modular Multiplication Based on Redundant Binary Representation
In this brief, Redundant Binary Representation (RBR) is applied in Montgomery modular multiplication (MMM) to eliminate the long carry chain and realize parallel computation. A novel MMM algorithm based on RBR is proposed. Based on the proposed algorithm, different sizes of high-performance and low-...
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Veröffentlicht in: | IEEE transactions on circuits and systems. II, Express briefs Express briefs, 2021-07, Vol.68 (7), p.2660-2664 |
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creator | Li, Bing Wang, Jinlei Ding, Guocheng Fu, Haisheng Lei, Bingjie Yang, Haitao Bi, Jiangang Lei, Shaochong |
description | In this brief, Redundant Binary Representation (RBR) is applied in Montgomery modular multiplication (MMM) to eliminate the long carry chain and realize parallel computation. A novel MMM algorithm based on RBR is proposed. Based on the proposed algorithm, different sizes of high-performance and low-cost Montgomery multipliers are implemented in TSMC CMOS process technology. The experimental results demonstrate that our design has significant advantages in terms of performance, area and Area-Time-Product over previous researches. It's worth mentioning that our 8192-bit Montgomery multiplier (TMSC 65nm) with 603MHz working frequency and 878.1K equivalent gates can complete the MMM in only 3403ns. |
doi_str_mv | 10.1109/TCSII.2021.3053630 |
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A novel MMM algorithm based on RBR is proposed. Based on the proposed algorithm, different sizes of high-performance and low-cost Montgomery multipliers are implemented in TSMC CMOS process technology. The experimental results demonstrate that our design has significant advantages in terms of performance, area and Area-Time-Product over previous researches. It's worth mentioning that our 8192-bit Montgomery multiplier (TMSC 65nm) with 603MHz working frequency and 878.1K equivalent gates can complete the MMM in only 3403ns.</description><identifier>ISSN: 1549-7747</identifier><identifier>EISSN: 1558-3791</identifier><identifier>DOI: 10.1109/TCSII.2021.3053630</identifier><identifier>CODEN: ICSPE5</identifier><language>eng</language><publisher>New York: IEEE</publisher><subject>Adders ; Algorithms ; ASIC ; Circuits and systems ; CMOS ; Delays ; ECC ; Elliptic curve cryptography ; Hardware ; Low cost ; Montgomery modular multiplication ; Multiplication ; Parallel processing ; Power systems ; redundant binary representation ; Representations ; RSA</subject><ispartof>IEEE transactions on circuits and systems. II, Express briefs, 2021-07, Vol.68 (7), p.2660-2664</ispartof><rights>Copyright The Institute of Electrical and Electronics Engineers, Inc. (IEEE) 2021</rights><lds50>peer_reviewed</lds50><woscitedreferencessubscribed>false</woscitedreferencessubscribed><citedby>FETCH-LOGICAL-c295t-fc9235d1e9e6f7480ecc8f68c0eaf21dc0b48c20314e0e1f00da7fe68815101a3</citedby><cites>FETCH-LOGICAL-c295t-fc9235d1e9e6f7480ecc8f68c0eaf21dc0b48c20314e0e1f00da7fe68815101a3</cites><orcidid>0000-0002-0113-5500 ; 0000-0002-4214-6863 ; 0000-0003-1400-4689</orcidid></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://ieeexplore.ieee.org/document/9333592$$EHTML$$P50$$Gieee$$H</linktohtml><link.rule.ids>314,780,784,796,27924,27925,54758</link.rule.ids><linktorsrc>$$Uhttps://ieeexplore.ieee.org/document/9333592$$EView_record_in_IEEE$$FView_record_in_$$GIEEE</linktorsrc></links><search><creatorcontrib>Li, Bing</creatorcontrib><creatorcontrib>Wang, Jinlei</creatorcontrib><creatorcontrib>Ding, Guocheng</creatorcontrib><creatorcontrib>Fu, Haisheng</creatorcontrib><creatorcontrib>Lei, Bingjie</creatorcontrib><creatorcontrib>Yang, Haitao</creatorcontrib><creatorcontrib>Bi, Jiangang</creatorcontrib><creatorcontrib>Lei, Shaochong</creatorcontrib><title>A High-Performance and Low-Cost Montgomery Modular Multiplication Based on Redundant Binary Representation</title><title>IEEE transactions on circuits and systems. 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II, Express briefs</jtitle></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Li, Bing</au><au>Wang, Jinlei</au><au>Ding, Guocheng</au><au>Fu, Haisheng</au><au>Lei, Bingjie</au><au>Yang, Haitao</au><au>Bi, Jiangang</au><au>Lei, Shaochong</au><format>journal</format><genre>article</genre><ristype>JOUR</ristype><atitle>A High-Performance and Low-Cost Montgomery Modular Multiplication Based on Redundant Binary Representation</atitle><jtitle>IEEE transactions on circuits and systems. II, Express briefs</jtitle><stitle>TCSII</stitle><date>2021-07-01</date><risdate>2021</risdate><volume>68</volume><issue>7</issue><spage>2660</spage><epage>2664</epage><pages>2660-2664</pages><issn>1549-7747</issn><eissn>1558-3791</eissn><coden>ICSPE5</coden><abstract>In this brief, Redundant Binary Representation (RBR) is applied in Montgomery modular multiplication (MMM) to eliminate the long carry chain and realize parallel computation. A novel MMM algorithm based on RBR is proposed. Based on the proposed algorithm, different sizes of high-performance and low-cost Montgomery multipliers are implemented in TSMC CMOS process technology. The experimental results demonstrate that our design has significant advantages in terms of performance, area and Area-Time-Product over previous researches. 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subjects | Adders Algorithms ASIC Circuits and systems CMOS Delays ECC Elliptic curve cryptography Hardware Low cost Montgomery modular multiplication Multiplication Parallel processing Power systems redundant binary representation Representations RSA |
title | A High-Performance and Low-Cost Montgomery Modular Multiplication Based on Redundant Binary Representation |
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