Analytical Modeling the Multi-Core Shared Cache Behavior With Considerations of Data-Sharing and Coherence

To mitigate the ever worsening "Power wall" and "Memory wall" problems, multi-core architectures with multi-level cache hierarchies have been widely accepted in modern processors. However, the complexity of the architectures makes modeling of shared caches extremely complex. In t...

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Veröffentlicht in:	IEEE access 2021, Vol.9, p.17728-17743
Hauptverfasser:	Ling, Ming, Lu, Xiaoqian, Wang, Guangmin, Ge, Jiancong
Format:	Artikel
Sprache:	eng
Schlagworte:	Analytical model Analytical models Coherence Complexity Computer architecture Configurations Data models data sharing Errors Hardware Hierarchies Mathematical analysis Mathematical models Modelling multi-core multi-level cache Multicore processing Program processors Simulation Upstream
Online-Zugang:	Volltext
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