A low-power 8-PAM serial-transceiver in 0.5 /spl mu/m digital CMOS

A CMOS multi-level (8-PAM) transceiver is described. Preemphasis is implemented without an increase in DAC resolution or digital computation. The receiver oversamples with three fully differential 3-bit ADCs. The device transmits at up to 1.3 Gb/s and has a measured BER of

Bibliographische Detailangaben

Hauptverfasser:	Foley, D.J., Flynn, M.P.
Format:	Tagungsbericht
Sprache:	eng
Schlagworte:	Bit error rate Circuits Clocks CMOS process Decoding Engines Logic Packaging Synthesizers Transceivers
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