Mapping TSN Traffic Scheduling and Shaping to FPGA-based Architecture

Time-Sensitive Networking (TSN), which evolves from the Ethernet standards, has been developed to ensure deterministic transmission in data networks. Asynchronous Traffic Shaping (ATS) extends the conventional synchronized TSN with an asynchronous scheduler to guarantee a bounded transmitting delay....

Ausführliche Beschreibung

Bibliographische Detailangaben

Veröffentlicht in:	IEEE access 2020-01, Vol.8, p.1-1
Hauptverfasser:	Zhou, Zifan, Berger, Michael Stubert, Yan, Ying
Format:	Artikel
Sprache:	eng
Schlagworte:	Configurations Ethernet Ethernet networks Field programmable gate arrays FPGA Hardware Logic gates Priority scheduling Real-time systems Resource utilization Scheduling Scheduling algorithm Switches Throughput
Online-Zugang:	Volltext
Tags:	Tag hinzufügen Keine Tags, Fügen Sie den ersten Tag hinzu!