A self-test methodology for IP cores in bus-based programmable SoCs

We present a novel test methodology for testing IP cores in SoCs with embedded processor cores. A test program is run on the processor core that generates and delivers test patterns to the target IP cores in the SoC and analyzes the test responses. This provides tremendous flexibility in the type of...

Ausführliche Beschreibung

Bibliographische Detailangaben

Hauptverfasser:	Jing-Reng Huang, Iyer, M.K., Kwang-Ting Cheng
Format:	Tagungsbericht
Sprache:	eng
Schlagworte:	Automatic testing Built-in self-test Circuit testing Delay Embedded software Pattern analysis Software testing System testing System-on-a-chip Test pattern generators
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