A method for measuring the cycle-to-cycle period jitter of high-frequency clock signals
This paper introduces the extended /spl Delta//spl phi/ method for measuring cycle-to-cycle period jitter in PLL outputs. The theoretical basis for this method is derived from the limited condition for the average period and analytic signal theory. Sinusoidal jitter measurements verify the relations...
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| creator | Yamaguchi, T.J. Soma, M. Halter, D. Raina, R. Nissen, J. Ishida, M. |
| description | This paper introduces the extended /spl Delta//spl phi/ method for measuring cycle-to-cycle period jitter in PLL outputs. The theoretical basis for this method is derived from the limited condition for the average period and analytic signal theory. Sinusoidal jitter measurements verify the relationship between cycle-to-cycle period jitter and timing jitter. To validate the method, experimental data from jitter measurements on a PowerPC/sup TM/ microprocessor is analyzed in the frequency domain. Comparisons of phase quantization errors are made between the extended /spl Delta//spl phi/ method and the conventional zero-crossing method. |
| doi_str_mv | 10.1109/VTS.2001.923425 |
| format | Conference Proceeding |
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The theoretical basis for this method is derived from the limited condition for the average period and analytic signal theory. Sinusoidal jitter measurements verify the relationship between cycle-to-cycle period jitter and timing jitter. To validate the method, experimental data from jitter measurements on a PowerPC/sup TM/ microprocessor is analyzed in the frequency domain. Comparisons of phase quantization errors are made between the extended /spl Delta//spl phi/ method and the conventional zero-crossing method.</description><identifier>ISBN: 9780769511221</identifier><identifier>ISBN: 0769511228</identifier><identifier>DOI: 10.1109/VTS.2001.923425</identifier><language>eng ; jpn</language><publisher>IEEE</publisher><subject>Clocks ; Electric variables measurement ; Frequency estimation ; Frequency measurement ; Microprocessors ; Phase measurement ; Phase noise ; Quantization ; Testing ; Timing jitter</subject><ispartof>Proceedings 19th IEEE VLSI Test Symposium. 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Comparisons of phase quantization errors are made between the extended /spl Delta//spl phi/ method and the conventional zero-crossing method.</description><subject>Clocks</subject><subject>Electric variables measurement</subject><subject>Frequency estimation</subject><subject>Frequency measurement</subject><subject>Microprocessors</subject><subject>Phase measurement</subject><subject>Phase noise</subject><subject>Quantization</subject><subject>Testing</subject><subject>Timing jitter</subject><isbn>9780769511221</isbn><isbn>0769511228</isbn><fulltext>true</fulltext><rsrctype>conference_proceeding</rsrctype><creationdate>2001</creationdate><recordtype>conference_proceeding</recordtype><sourceid>6IE</sourceid><sourceid>RIE</sourceid><recordid>eNotj7tqwzAARQWl0JJ6LnTSD8jV05LGEPqCQIem7Rj0tJU6diorQ_6-JuldzhkuFy4A9wTXhGD9-LX5qCnGpNaUcSquQKWlwrLRghBKyQ2opmmH53DBJRW34HsJ96F0o4dxzLOa6ZjT0MLSBehOrg-ojOgs8BBymnu7VErIcIywS22HYg6_xzC4E3T96H7glNrB9NMduI4zQvXPBfh8ftqsXtH6_eVttVyjRCQuSFlFtMM4UqWMdZw1omHGem59INYpRzxTTmkqpGfUSW-ppqbBPlpuGi_YAjxcdlMIYXvIaW_yaXt5z_4AwrVQhQ</recordid><startdate>2001</startdate><enddate>2001</enddate><creator>Yamaguchi, T.J.</creator><creator>Soma, M.</creator><creator>Halter, D.</creator><creator>Raina, R.</creator><creator>Nissen, J.</creator><creator>Ishida, M.</creator><general>IEEE</general><scope>6IE</scope><scope>6IL</scope><scope>CBEJK</scope><scope>RIE</scope><scope>RIL</scope></search><sort><creationdate>2001</creationdate><title>A method for measuring the cycle-to-cycle period jitter of high-frequency clock signals</title><author>Yamaguchi, T.J. ; Soma, M. ; Halter, D. ; Raina, R. ; Nissen, J. ; Ishida, M.</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-i170t-8b819c00f288abc436563abd4bde1bc8c1d38c89257d32c7db292a60dfb4a6d53</frbrgroupid><rsrctype>conference_proceedings</rsrctype><prefilter>conference_proceedings</prefilter><language>eng ; jpn</language><creationdate>2001</creationdate><topic>Clocks</topic><topic>Electric variables measurement</topic><topic>Frequency estimation</topic><topic>Frequency measurement</topic><topic>Microprocessors</topic><topic>Phase measurement</topic><topic>Phase noise</topic><topic>Quantization</topic><topic>Testing</topic><topic>Timing jitter</topic><toplevel>online_resources</toplevel><creatorcontrib>Yamaguchi, T.J.</creatorcontrib><creatorcontrib>Soma, M.</creatorcontrib><creatorcontrib>Halter, D.</creatorcontrib><creatorcontrib>Raina, R.</creatorcontrib><creatorcontrib>Nissen, J.</creatorcontrib><creatorcontrib>Ishida, M.</creatorcontrib><collection>IEEE Electronic Library (IEL) Conference Proceedings</collection><collection>IEEE Proceedings Order Plan All Online (POP All Online) 1998-present by volume</collection><collection>IEEE Xplore All Conference Proceedings</collection><collection>IEEE Electronic Library (IEL)</collection><collection>IEEE Proceedings Order Plans (POP All) 1998-Present</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Yamaguchi, T.J.</au><au>Soma, M.</au><au>Halter, D.</au><au>Raina, R.</au><au>Nissen, J.</au><au>Ishida, M.</au><format>book</format><genre>proceeding</genre><ristype>CONF</ristype><atitle>A method for measuring the cycle-to-cycle period jitter of high-frequency clock signals</atitle><btitle>Proceedings 19th IEEE VLSI Test Symposium. VTS 2001</btitle><stitle>VTS</stitle><date>2001</date><risdate>2001</risdate><spage>102</spage><epage>110</epage><pages>102-110</pages><isbn>9780769511221</isbn><isbn>0769511228</isbn><abstract>This paper introduces the extended /spl Delta//spl phi/ method for measuring cycle-to-cycle period jitter in PLL outputs. The theoretical basis for this method is derived from the limited condition for the average period and analytic signal theory. Sinusoidal jitter measurements verify the relationship between cycle-to-cycle period jitter and timing jitter. To validate the method, experimental data from jitter measurements on a PowerPC/sup TM/ microprocessor is analyzed in the frequency domain. Comparisons of phase quantization errors are made between the extended /spl Delta//spl phi/ method and the conventional zero-crossing method.</abstract><pub>IEEE</pub><doi>10.1109/VTS.2001.923425</doi><tpages>9</tpages></addata></record> |
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| ispartof | Proceedings 19th IEEE VLSI Test Symposium. VTS 2001, 2001, p.102-110 |
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| language | eng ; jpn |
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| source | IEEE Electronic Library (IEL) Conference Proceedings |
| subjects | Clocks Electric variables measurement Frequency estimation Frequency measurement Microprocessors Phase measurement Phase noise Quantization Testing Timing jitter |
| title | A method for measuring the cycle-to-cycle period jitter of high-frequency clock signals |
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