A 10-bit, 2.5-V, 40 M sample/s, pipelined analog-to-digital converter in 0.6-/spl mu/m CMOS
A high-speed, low-voltage pipelined analog-to-digital converter is presented. It achieves 58 dB SNDR with full-scale Nyquist rate sinusoidal input and conversion rate of 40 MHz with a power supply of 2.25 V. A 1.5 bit per stage architecture is used for all the stages except the first one. The first...
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| creator | Nejati, B. Shoaei, O. |
| description | A high-speed, low-voltage pipelined analog-to-digital converter is presented. It achieves 58 dB SNDR with full-scale Nyquist rate sinusoidal input and conversion rate of 40 MHz with a power supply of 2.25 V. A 1.5 bit per stage architecture is used for all the stages except the first one. The first stage employs more comparators to reduce the signal swing at the output of the stage, hence relaxes conditions on the op-amp transistor sizes in the subsequent stages. Simulation results have been checked with all process corners from -40/spl deg/C to +120/spl deg/C and /spl plusmn/15% variation in poly-poly capacitor sizes. |
| doi_str_mv | 10.1109/ISCAS.2001.921921 |
| format | Conference Proceeding |
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No.01CH37196)</title><addtitle>ISCAS</addtitle><description>A high-speed, low-voltage pipelined analog-to-digital converter is presented. It achieves 58 dB SNDR with full-scale Nyquist rate sinusoidal input and conversion rate of 40 MHz with a power supply of 2.25 V. A 1.5 bit per stage architecture is used for all the stages except the first one. The first stage employs more comparators to reduce the signal swing at the output of the stage, hence relaxes conditions on the op-amp transistor sizes in the subsequent stages. Simulation results have been checked with all process corners from -40/spl deg/C to +120/spl deg/C and /spl plusmn/15% variation in poly-poly capacitor sizes.</description><subject>Analog-digital conversion</subject><subject>Capacitors</subject><subject>CMOS process</subject><subject>Digital signal processing</subject><subject>Operational amplifiers</subject><subject>Pipelines</subject><subject>Power dissipation</subject><subject>Power supplies</subject><subject>Sampling methods</subject><subject>Transfer functions</subject><isbn>9780780366855</isbn><isbn>0780366859</isbn><fulltext>true</fulltext><rsrctype>conference_proceeding</rsrctype><creationdate>2001</creationdate><recordtype>conference_proceeding</recordtype><sourceid>6IE</sourceid><sourceid>RIE</sourceid><recordid>eNp9jsGKwjAURQMyoDj9AF29D2jSlzatdilFcRbiouLGhUR9SiRtQ1MF_96Crudw4Czu5jI2kSikxDz6K4tFKWJEKfJY9g5YkM_m2Jtk2TxNhyzw_o49KlVKJSN2WIBEfjJdCLFI-T4EhbABrytnKfIhOOPImpouoGttmxvvGn4xN9NpC-emflLbUQumBhQZj7yzUD2iCorNtvxlP1dtPQXfjtl0tdwVa26I6OhaU-n2dfw8Tf4d33oWPhU</recordid><startdate>2001</startdate><enddate>2001</enddate><creator>Nejati, B.</creator><creator>Shoaei, O.</creator><general>IEEE</general><scope>6IE</scope><scope>6IH</scope><scope>CBEJK</scope><scope>RIE</scope><scope>RIO</scope></search><sort><creationdate>2001</creationdate><title>A 10-bit, 2.5-V, 40 M sample/s, pipelined analog-to-digital converter in 0.6-/spl mu/m CMOS</title><author>Nejati, B. ; Shoaei, O.</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-ieee_primary_9219213</frbrgroupid><rsrctype>conference_proceedings</rsrctype><prefilter>conference_proceedings</prefilter><language>eng</language><creationdate>2001</creationdate><topic>Analog-digital conversion</topic><topic>Capacitors</topic><topic>CMOS process</topic><topic>Digital signal processing</topic><topic>Operational amplifiers</topic><topic>Pipelines</topic><topic>Power dissipation</topic><topic>Power supplies</topic><topic>Sampling methods</topic><topic>Transfer functions</topic><toplevel>online_resources</toplevel><creatorcontrib>Nejati, B.</creatorcontrib><creatorcontrib>Shoaei, O.</creatorcontrib><collection>IEEE Electronic Library (IEL) Conference Proceedings</collection><collection>IEEE Proceedings Order Plan (POP) 1998-present by volume</collection><collection>IEEE Xplore All Conference Proceedings</collection><collection>IEEE Electronic Library (IEL)</collection><collection>IEEE Proceedings Order Plans (POP) 1998-present</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Nejati, B.</au><au>Shoaei, O.</au><format>book</format><genre>proceeding</genre><ristype>CONF</ristype><atitle>A 10-bit, 2.5-V, 40 M sample/s, pipelined analog-to-digital converter in 0.6-/spl mu/m CMOS</atitle><btitle>ISCAS 2001. The 2001 IEEE International Symposium on Circuits and Systems (Cat. No.01CH37196)</btitle><stitle>ISCAS</stitle><date>2001</date><risdate>2001</risdate><volume>1</volume><spage>576</spage><epage>579 vol. 1</epage><pages>576-579 vol. 1</pages><isbn>9780780366855</isbn><isbn>0780366859</isbn><abstract>A high-speed, low-voltage pipelined analog-to-digital converter is presented. It achieves 58 dB SNDR with full-scale Nyquist rate sinusoidal input and conversion rate of 40 MHz with a power supply of 2.25 V. A 1.5 bit per stage architecture is used for all the stages except the first one. The first stage employs more comparators to reduce the signal swing at the output of the stage, hence relaxes conditions on the op-amp transistor sizes in the subsequent stages. Simulation results have been checked with all process corners from -40/spl deg/C to +120/spl deg/C and /spl plusmn/15% variation in poly-poly capacitor sizes.</abstract><pub>IEEE</pub><doi>10.1109/ISCAS.2001.921921</doi></addata></record> |
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| identifier | ISBN: 9780780366855 |
| ispartof | ISCAS 2001. The 2001 IEEE International Symposium on Circuits and Systems (Cat. No.01CH37196), 2001, Vol.1, p.576-579 vol. 1 |
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| language | eng |
| recordid | cdi_ieee_primary_921921 |
| source | IEEE Electronic Library (IEL) Conference Proceedings |
| subjects | Analog-digital conversion Capacitors CMOS process Digital signal processing Operational amplifiers Pipelines Power dissipation Power supplies Sampling methods Transfer functions |
| title | A 10-bit, 2.5-V, 40 M sample/s, pipelined analog-to-digital converter in 0.6-/spl mu/m CMOS |
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