A 67-fsrms Jitter, −130 dBc/Hz In-Band Phase Noise, −256-dB FoM Reference Oversampling Digital PLL With Proportional Path Timing Control

An LC oscillator-based reference oversampling PLL (OSPLL) is proposed in this work. An LC digitally controlled oscillator (DCO) with proportional path gain profile control and DCO tuning pulse timing control scheme is proposed for optimal phase noise. Designed in 28-nm CMOS process, the proposed PLL...

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Veröffentlicht in:	IEEE solid-state circuits letters 2020, Vol.3, p.430-433
Hauptverfasser:	Seol, Ji-Hwan, Choo, Kyojin, Blaauw, David, Sylvester, Dennis, Jang, Taekwang
Format:	Artikel
Sprache:	eng
Schlagworte:	CMOS Delay lines Digital controlled oscillator digital PLL frequency synthesizer Jitter Noise Noise levels Oversampling Phase locked loops Phase locked systems Phase noise Power consumption reference oversampling PLL reference spur Solid state circuits Switches Timing Vibration
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