A 67-fsrms Jitter, −130 dBc/Hz In-Band Phase Noise, −256-dB FoM Reference Oversampling Digital PLL With Proportional Path Timing Control
An LC oscillator-based reference oversampling PLL (OSPLL) is proposed in this work. An LC digitally controlled oscillator (DCO) with proportional path gain profile control and DCO tuning pulse timing control scheme is proposed for optimal phase noise. Designed in 28-nm CMOS process, the proposed PLL...
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| Veröffentlicht in: | IEEE solid-state circuits letters 2020, Vol.3, p.430-433 |
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| container_title | IEEE solid-state circuits letters |
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| creator | Seol, Ji-Hwan Choo, Kyojin Blaauw, David Sylvester, Dennis Jang, Taekwang |
| description | An LC oscillator-based reference oversampling PLL (OSPLL) is proposed in this work. An LC digitally controlled oscillator (DCO) with proportional path gain profile control and DCO tuning pulse timing control scheme is proposed for optimal phase noise. Designed in 28-nm CMOS process, the proposed PLL achieves 67.1-fs RMS-jitter with 5.2-mW power consumption, which translates to −256-dB FoM. The in-band phase noise of the PLL is −130 dBc/Hz at 4-GHz output frequency. The reference spur of the proposed PLL is −78 dBc. |
| doi_str_mv | 10.1109/LSSC.2020.3025142 |
| format | Article |
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An LC digitally controlled oscillator (DCO) with proportional path gain profile control and DCO tuning pulse timing control scheme is proposed for optimal phase noise. Designed in 28-nm CMOS process, the proposed PLL achieves 67.1-fs RMS-jitter with 5.2-mW power consumption, which translates to −256-dB FoM. The in-band phase noise of the PLL is −130 dBc/Hz at 4-GHz output frequency. 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An LC digitally controlled oscillator (DCO) with proportional path gain profile control and DCO tuning pulse timing control scheme is proposed for optimal phase noise. Designed in 28-nm CMOS process, the proposed PLL achieves 67.1-fs RMS-jitter with 5.2-mW power consumption, which translates to −256-dB FoM. The in-band phase noise of the PLL is −130 dBc/Hz at 4-GHz output frequency. The reference spur of the proposed PLL is −78 dBc.</description><subject>CMOS</subject><subject>Delay lines</subject><subject>Digital controlled oscillator</subject><subject>digital PLL</subject><subject>frequency synthesizer</subject><subject>Jitter</subject><subject>Noise</subject><subject>Noise levels</subject><subject>Oversampling</subject><subject>Phase locked loops</subject><subject>Phase locked systems</subject><subject>Phase noise</subject><subject>Power consumption</subject><subject>reference oversampling PLL</subject><subject>reference spur</subject><subject>Solid state circuits</subject><subject>Switches</subject><subject>Timing</subject><subject>Vibration</subject><issn>2573-9603</issn><fulltext>true</fulltext><rsrctype>article</rsrctype><creationdate>2020</creationdate><recordtype>article</recordtype><sourceid>RIE</sourceid><recordid>eNotkM1OwkAURicmJhLkAYybSdxamL-2M0tAEUwVIiQuydC5hSG0gzPFRJ_AhSsf0Sexioubm5ycfPfmQ-iCki6lRPWy-XzYZYSRLicspoKdoBaLUx6phPAz1AlhSwihiiacyBb67OMkjYrgy4DvbV2Dv8bfH1-UE2wGeW_8jidVNNCVwbONDoAfnQ3wp7A4icwAj9wDfoICPFQ54Okr-KDL_c5Wa3xj17bWOzzLMvxs6w2eebd3vrau-qW6IQtb_ppDV9Xe7c7RaaF3ATr_u40Wo9vFcBxl07vJsJ9FVsg0YonhUmieQ0oFp7BSwpBmDFUqXwkRi3TFiZGFBCPlSopYcxlrySBmjOuCt9HVMXbv3csBQr3cuoNvfgpLJmJKlSBNYW10ebQsACz33pbavy1Vc0QRwX8A9YRrhw</recordid><startdate>2020</startdate><enddate>2020</enddate><creator>Seol, Ji-Hwan</creator><creator>Choo, Kyojin</creator><creator>Blaauw, David</creator><creator>Sylvester, Dennis</creator><creator>Jang, Taekwang</creator><general>IEEE</general><general>The Institute of Electrical and Electronics Engineers, Inc. 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An LC digitally controlled oscillator (DCO) with proportional path gain profile control and DCO tuning pulse timing control scheme is proposed for optimal phase noise. Designed in 28-nm CMOS process, the proposed PLL achieves 67.1-fs RMS-jitter with 5.2-mW power consumption, which translates to −256-dB FoM. The in-band phase noise of the PLL is −130 dBc/Hz at 4-GHz output frequency. The reference spur of the proposed PLL is −78 dBc.</abstract><cop>Piscataway</cop><pub>IEEE</pub><doi>10.1109/LSSC.2020.3025142</doi><tpages>4</tpages><orcidid>https://orcid.org/0000-0001-8119-094X</orcidid><orcidid>https://orcid.org/0000-0001-6744-7075</orcidid><orcidid>https://orcid.org/0000-0002-8081-0040</orcidid><orcidid>https://orcid.org/0000-0003-2598-0458</orcidid><orcidid>https://orcid.org/0000-0002-4651-0677</orcidid></addata></record> |
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| ispartof | IEEE solid-state circuits letters, 2020, Vol.3, p.430-433 |
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| language | eng |
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| source | IEEE Electronic Library (IEL) |
| subjects | CMOS Delay lines Digital controlled oscillator digital PLL frequency synthesizer Jitter Noise Noise levels Oversampling Phase locked loops Phase locked systems Phase noise Power consumption reference oversampling PLL reference spur Solid state circuits Switches Timing Vibration |
| title | A 67-fsrms Jitter, −130 dBc/Hz In-Band Phase Noise, −256-dB FoM Reference Oversampling Digital PLL With Proportional Path Timing Control |
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