1.6 Gb/s/pin 4-PAM signaling and circuits for a multidrop bus

A 1.6 Gb/s/pin 4-pulse-amplitude-modulated (PAM) multidrop signaling system has been designed. The motivation for multi-PAM signaling is discussed. The system uses single-ended+reference current-mode signaling with three dc references for maximum bandwidth per pin. A test chip with six I/O pins was...

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Veröffentlicht in:	IEEE journal of solid-state circuits 2001-05, Vol.36 (5), p.752-760
Hauptverfasser:	Zerbe, J.L., Chau, P.S., Werner, C.W., Thrush, T.P., Liaw, H.J., Garlepp, B.W., Donnelly, K.S.
Format:	Artikel
Sprache:	eng
Schlagworte:	Architecture Bandwidth Buses (vehicles) Checkers Chip formation Circuit testing Circuits Communication system signaling Devices Direct current Electric potential Pins Semiconductor device measurement Signal design Signal to noise ratio System testing System-on-a-chip Transmitters
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