1.6 Gb/s/pin 4-PAM signaling and circuits for a multidrop bus
A 1.6 Gb/s/pin 4-pulse-amplitude-modulated (PAM) multidrop signaling system has been designed. The motivation for multi-PAM signaling is discussed. The system uses single-ended+reference current-mode signaling with three dc references for maximum bandwidth per pin. A test chip with six I/O pins was...
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| Veröffentlicht in: | IEEE journal of solid-state circuits 2001-05, Vol.36 (5), p.752-760 |
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| container_end_page | 760 |
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| container_title | IEEE journal of solid-state circuits |
| container_volume | 36 |
| creator | Zerbe, J.L. Chau, P.S. Werner, C.W. Thrush, T.P. Liaw, H.J. Garlepp, B.W. Donnelly, K.S. |
| description | A 1.6 Gb/s/pin 4-pulse-amplitude-modulated (PAM) multidrop signaling system has been designed. The motivation for multi-PAM signaling is discussed. The system uses single-ended+reference current-mode signaling with three dc references for maximum bandwidth per pin. A test chip with six I/O pins was fabricated in 0.35-/spl mu/m CMOS and tested in a 28-/spl Omega/ evaluation system using on-chip 2/sup 10/ pseudorandom bit sequence (PRBS) generator/checkers. Two different 4-PAM transmitter structures were designed and measured. A high-gain windowed integrating input receiver with wide common-mode range was designed in order to improve signal-to-noise ratio when operating with smaller 4-PAM input levels. Gray coding allowed a folded preamplifier architecture to be used in the LSB input receiver to minimize area and power. In-system margins are measured via system voltage and timing shmoos with a master communicating with two slave devices. |
| doi_str_mv | 10.1109/4.918912 |
| format | Article |
| fullrecord | <record><control><sourceid>proquest_RIE</sourceid><recordid>TN_cdi_ieee_primary_918912</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><ieee_id>918912</ieee_id><sourcerecordid>2633045271</sourcerecordid><originalsourceid>FETCH-LOGICAL-c365t-5cabeb6abc6c0165b5dc8a8de0149dfb7d6f9f006569e84fb701cfb9223819f3</originalsourceid><addsrcrecordid>eNqN0bFOwzAQAFALgUQpSMxMFgOwpPU5sWMPDFUFBakIhg5skePYlas0CXYy8PcYpWJgQEzW-Z7uTncIXQKZARA5z2YShAR6hCbAmEggT9-P0YQQEImkhJyisxB2McwyARN0DzOOV-U8zDvX4Cx5W7zg4LaNql2zxaqpsHZeD64P2LYeK7wf6t5Vvu1wOYRzdGJVHczF4Z2izePDZvmUrF9Xz8vFOtEpZ33CtCpNyVWpuSbAWckqLZSoTJxCVrbMK26lJYQzLo3I4gcBbUtJaSpA2nSKbseynW8_BhP6Yu-CNnWtGtMOoZCQcc5pzqO8-VNSEfch6T8g5yllRER4_Qvu2sHH_cS2Mg7McpAR3Y1I-zYEb2zRebdX_rMAUnyfpciK8SyRXo3UGWN-2CH5BfhChF4</addsrcrecordid><sourcetype>Aggregation Database</sourcetype><iscdi>true</iscdi><recordtype>article</recordtype><pqid>996565719</pqid></control><display><type>article</type><title>1.6 Gb/s/pin 4-PAM signaling and circuits for a multidrop bus</title><source>IEEE Electronic Library (IEL)</source><creator>Zerbe, J.L. ; Chau, P.S. ; Werner, C.W. ; Thrush, T.P. ; Liaw, H.J. ; Garlepp, B.W. ; Donnelly, K.S.</creator><creatorcontrib>Zerbe, J.L. ; Chau, P.S. ; Werner, C.W. ; Thrush, T.P. ; Liaw, H.J. ; Garlepp, B.W. ; Donnelly, K.S.</creatorcontrib><description>A 1.6 Gb/s/pin 4-pulse-amplitude-modulated (PAM) multidrop signaling system has been designed. The motivation for multi-PAM signaling is discussed. The system uses single-ended+reference current-mode signaling with three dc references for maximum bandwidth per pin. A test chip with six I/O pins was fabricated in 0.35-/spl mu/m CMOS and tested in a 28-/spl Omega/ evaluation system using on-chip 2/sup 10/ pseudorandom bit sequence (PRBS) generator/checkers. Two different 4-PAM transmitter structures were designed and measured. A high-gain windowed integrating input receiver with wide common-mode range was designed in order to improve signal-to-noise ratio when operating with smaller 4-PAM input levels. Gray coding allowed a folded preamplifier architecture to be used in the LSB input receiver to minimize area and power. In-system margins are measured via system voltage and timing shmoos with a master communicating with two slave devices.</description><identifier>ISSN: 0018-9200</identifier><identifier>EISSN: 1558-173X</identifier><identifier>DOI: 10.1109/4.918912</identifier><identifier>CODEN: IJSCBC</identifier><language>eng</language><publisher>New York: IEEE</publisher><subject>Architecture ; Bandwidth ; Buses (vehicles) ; Checkers ; Chip formation ; Circuit testing ; Circuits ; Communication system signaling ; Devices ; Direct current ; Electric potential ; Pins ; Semiconductor device measurement ; Signal design ; Signal to noise ratio ; System testing ; System-on-a-chip ; Transmitters</subject><ispartof>IEEE journal of solid-state circuits, 2001-05, Vol.36 (5), p.752-760</ispartof><rights>Copyright The Institute of Electrical and Electronics Engineers, Inc. (IEEE) 2001</rights><lds50>peer_reviewed</lds50><woscitedreferencessubscribed>false</woscitedreferencessubscribed><citedby>FETCH-LOGICAL-c365t-5cabeb6abc6c0165b5dc8a8de0149dfb7d6f9f006569e84fb701cfb9223819f3</citedby><cites>FETCH-LOGICAL-c365t-5cabeb6abc6c0165b5dc8a8de0149dfb7d6f9f006569e84fb701cfb9223819f3</cites></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://ieeexplore.ieee.org/document/918912$$EHTML$$P50$$Gieee$$H</linktohtml><link.rule.ids>314,780,784,796,27924,27925,54758</link.rule.ids><linktorsrc>$$Uhttps://ieeexplore.ieee.org/document/918912$$EView_record_in_IEEE$$FView_record_in_$$GIEEE</linktorsrc></links><search><creatorcontrib>Zerbe, J.L.</creatorcontrib><creatorcontrib>Chau, P.S.</creatorcontrib><creatorcontrib>Werner, C.W.</creatorcontrib><creatorcontrib>Thrush, T.P.</creatorcontrib><creatorcontrib>Liaw, H.J.</creatorcontrib><creatorcontrib>Garlepp, B.W.</creatorcontrib><creatorcontrib>Donnelly, K.S.</creatorcontrib><title>1.6 Gb/s/pin 4-PAM signaling and circuits for a multidrop bus</title><title>IEEE journal of solid-state circuits</title><addtitle>JSSC</addtitle><description>A 1.6 Gb/s/pin 4-pulse-amplitude-modulated (PAM) multidrop signaling system has been designed. The motivation for multi-PAM signaling is discussed. The system uses single-ended+reference current-mode signaling with three dc references for maximum bandwidth per pin. A test chip with six I/O pins was fabricated in 0.35-/spl mu/m CMOS and tested in a 28-/spl Omega/ evaluation system using on-chip 2/sup 10/ pseudorandom bit sequence (PRBS) generator/checkers. Two different 4-PAM transmitter structures were designed and measured. A high-gain windowed integrating input receiver with wide common-mode range was designed in order to improve signal-to-noise ratio when operating with smaller 4-PAM input levels. Gray coding allowed a folded preamplifier architecture to be used in the LSB input receiver to minimize area and power. In-system margins are measured via system voltage and timing shmoos with a master communicating with two slave devices.</description><subject>Architecture</subject><subject>Bandwidth</subject><subject>Buses (vehicles)</subject><subject>Checkers</subject><subject>Chip formation</subject><subject>Circuit testing</subject><subject>Circuits</subject><subject>Communication system signaling</subject><subject>Devices</subject><subject>Direct current</subject><subject>Electric potential</subject><subject>Pins</subject><subject>Semiconductor device measurement</subject><subject>Signal design</subject><subject>Signal to noise ratio</subject><subject>System testing</subject><subject>System-on-a-chip</subject><subject>Transmitters</subject><issn>0018-9200</issn><issn>1558-173X</issn><fulltext>true</fulltext><rsrctype>article</rsrctype><creationdate>2001</creationdate><recordtype>article</recordtype><sourceid>RIE</sourceid><recordid>eNqN0bFOwzAQAFALgUQpSMxMFgOwpPU5sWMPDFUFBakIhg5skePYlas0CXYy8PcYpWJgQEzW-Z7uTncIXQKZARA5z2YShAR6hCbAmEggT9-P0YQQEImkhJyisxB2McwyARN0DzOOV-U8zDvX4Cx5W7zg4LaNql2zxaqpsHZeD64P2LYeK7wf6t5Vvu1wOYRzdGJVHczF4Z2izePDZvmUrF9Xz8vFOtEpZ33CtCpNyVWpuSbAWckqLZSoTJxCVrbMK26lJYQzLo3I4gcBbUtJaSpA2nSKbseynW8_BhP6Yu-CNnWtGtMOoZCQcc5pzqO8-VNSEfch6T8g5yllRER4_Qvu2sHH_cS2Mg7McpAR3Y1I-zYEb2zRebdX_rMAUnyfpciK8SyRXo3UGWN-2CH5BfhChF4</recordid><startdate>20010501</startdate><enddate>20010501</enddate><creator>Zerbe, J.L.</creator><creator>Chau, P.S.</creator><creator>Werner, C.W.</creator><creator>Thrush, T.P.</creator><creator>Liaw, H.J.</creator><creator>Garlepp, B.W.</creator><creator>Donnelly, K.S.</creator><general>IEEE</general><general>The Institute of Electrical and Electronics Engineers, Inc. (IEEE)</general><scope>RIA</scope><scope>RIE</scope><scope>AAYXX</scope><scope>CITATION</scope><scope>7SP</scope><scope>8FD</scope><scope>L7M</scope><scope>7U5</scope><scope>F28</scope><scope>FR3</scope><scope>KR7</scope></search><sort><creationdate>20010501</creationdate><title>1.6 Gb/s/pin 4-PAM signaling and circuits for a multidrop bus</title><author>Zerbe, J.L. ; Chau, P.S. ; Werner, C.W. ; Thrush, T.P. ; Liaw, H.J. ; Garlepp, B.W. ; Donnelly, K.S.</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-c365t-5cabeb6abc6c0165b5dc8a8de0149dfb7d6f9f006569e84fb701cfb9223819f3</frbrgroupid><rsrctype>articles</rsrctype><prefilter>articles</prefilter><language>eng</language><creationdate>2001</creationdate><topic>Architecture</topic><topic>Bandwidth</topic><topic>Buses (vehicles)</topic><topic>Checkers</topic><topic>Chip formation</topic><topic>Circuit testing</topic><topic>Circuits</topic><topic>Communication system signaling</topic><topic>Devices</topic><topic>Direct current</topic><topic>Electric potential</topic><topic>Pins</topic><topic>Semiconductor device measurement</topic><topic>Signal design</topic><topic>Signal to noise ratio</topic><topic>System testing</topic><topic>System-on-a-chip</topic><topic>Transmitters</topic><toplevel>peer_reviewed</toplevel><toplevel>online_resources</toplevel><creatorcontrib>Zerbe, J.L.</creatorcontrib><creatorcontrib>Chau, P.S.</creatorcontrib><creatorcontrib>Werner, C.W.</creatorcontrib><creatorcontrib>Thrush, T.P.</creatorcontrib><creatorcontrib>Liaw, H.J.</creatorcontrib><creatorcontrib>Garlepp, B.W.</creatorcontrib><creatorcontrib>Donnelly, K.S.</creatorcontrib><collection>IEEE All-Society Periodicals Package (ASPP) 1998-Present</collection><collection>IEEE Electronic Library (IEL)</collection><collection>CrossRef</collection><collection>Electronics & Communications Abstracts</collection><collection>Technology Research Database</collection><collection>Advanced Technologies Database with Aerospace</collection><collection>Solid State and Superconductivity Abstracts</collection><collection>ANTE: Abstracts in New Technology & Engineering</collection><collection>Engineering Research Database</collection><collection>Civil Engineering Abstracts</collection><jtitle>IEEE journal of solid-state circuits</jtitle></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Zerbe, J.L.</au><au>Chau, P.S.</au><au>Werner, C.W.</au><au>Thrush, T.P.</au><au>Liaw, H.J.</au><au>Garlepp, B.W.</au><au>Donnelly, K.S.</au><format>journal</format><genre>article</genre><ristype>JOUR</ristype><atitle>1.6 Gb/s/pin 4-PAM signaling and circuits for a multidrop bus</atitle><jtitle>IEEE journal of solid-state circuits</jtitle><stitle>JSSC</stitle><date>2001-05-01</date><risdate>2001</risdate><volume>36</volume><issue>5</issue><spage>752</spage><epage>760</epage><pages>752-760</pages><issn>0018-9200</issn><eissn>1558-173X</eissn><coden>IJSCBC</coden><abstract>A 1.6 Gb/s/pin 4-pulse-amplitude-modulated (PAM) multidrop signaling system has been designed. The motivation for multi-PAM signaling is discussed. The system uses single-ended+reference current-mode signaling with three dc references for maximum bandwidth per pin. A test chip with six I/O pins was fabricated in 0.35-/spl mu/m CMOS and tested in a 28-/spl Omega/ evaluation system using on-chip 2/sup 10/ pseudorandom bit sequence (PRBS) generator/checkers. Two different 4-PAM transmitter structures were designed and measured. A high-gain windowed integrating input receiver with wide common-mode range was designed in order to improve signal-to-noise ratio when operating with smaller 4-PAM input levels. Gray coding allowed a folded preamplifier architecture to be used in the LSB input receiver to minimize area and power. In-system margins are measured via system voltage and timing shmoos with a master communicating with two slave devices.</abstract><cop>New York</cop><pub>IEEE</pub><doi>10.1109/4.918912</doi><tpages>9</tpages></addata></record> |
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| source | IEEE Electronic Library (IEL) |
| subjects | Architecture Bandwidth Buses (vehicles) Checkers Chip formation Circuit testing Circuits Communication system signaling Devices Direct current Electric potential Pins Semiconductor device measurement Signal design Signal to noise ratio System testing System-on-a-chip Transmitters |
| title | 1.6 Gb/s/pin 4-PAM signaling and circuits for a multidrop bus |
| url | https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2024-12-23T13%3A56%3A36IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-proquest_RIE&rft_val_fmt=info:ofi/fmt:kev:mtx:journal&rft.genre=article&rft.atitle=1.6%20Gb/s/pin%204-PAM%20signaling%20and%20circuits%20for%20a%20multidrop%20bus&rft.jtitle=IEEE%20journal%20of%20solid-state%20circuits&rft.au=Zerbe,%20J.L.&rft.date=2001-05-01&rft.volume=36&rft.issue=5&rft.spage=752&rft.epage=760&rft.pages=752-760&rft.issn=0018-9200&rft.eissn=1558-173X&rft.coden=IJSCBC&rft_id=info:doi/10.1109/4.918912&rft_dat=%3Cproquest_RIE%3E2633045271%3C/proquest_RIE%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_pqid=996565719&rft_id=info:pmid/&rft_ieee_id=918912&rfr_iscdi=true |