Chip-level substrate noise analysis with network reduction by fundamental matrix computation

The fundamental matrix (F-matrix) based substrate mesh reduction technique is incorporated in a chip-level substrate noise simulation methodology. A system-level equivalent circuit model of a 0.6 /spl mu/m CMOS substrate noise evaluation chip demonstrates simulation errors of less than 15% by compar...

Ausführliche Beschreibung

Bibliographische Detailangaben

Hauptverfasser:	Murasaka, Y., Nagata, M., Ohmoto, T., Morie, T., Iwata, A.
Format:	Tagungsbericht
Sprache:	eng
Schlagworte:	Analytical models Circuit noise Circuit simulation Computer networks Equivalent circuits Noise generators Noise measurement Noise reduction Semiconductor device modeling Voltage
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