A 0.04% BER Strong PUF With Cell-Bias-Based CRPs Filtering and Background Offset Calibration
This paper presents a low bit error rate (BER) strong PUF based on the dynamically amplified subthreshold current array (DA-SCA) with cell-bias-based challenge-response-pairs (CRPs) filtering method. The highly nonlinear subthreshold characteristic of the DA-SCA ensures a strong resilience to machin...
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Veröffentlicht in: | IEEE transactions on circuits and systems. I, Regular papers Regular papers, 2020-11, Vol.67 (11), p.3853-3865 |
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creator | Liu, Jiahao Zhu, Yan Chan, Chi-Hang Martins, Rui Paulo |
description | This paper presents a low bit error rate (BER) strong PUF based on the dynamically amplified subthreshold current array (DA-SCA) with cell-bias-based challenge-response-pairs (CRPs) filtering method. The highly nonlinear subthreshold characteristic of the DA-SCA ensures a strong resilience to machine learning (ML) attacks and it simultaneously achieves low power and compact area. The current difference of two SCAs originated by the manufacturing process is amplified and converted into a voltage difference which is further digitized by the background offset-calibrated oscillator collapse-based comparator. Fabricated in 65 nm CMOS LP technology, the 64-bit DA-SCA PUF shows an average BER of 4.7% in the worst case for the temperature range of −20 to 80° and a supply variation of ±10%. Moreover, the proposed cell-bias-based CRPs filtering method dramatically suppresses the BER to 0.04% while discarding only 9.5% CRPs. The power consumption of the proposed PUF is merely 2.4~\mu \text{W} at 125 Kb/s and it occupies 0.024 mm 2 , including the on-chip calibration circuit. The proposed PUF demonstrates resistance against machine learning (ML) attacks across 100K training samples, limiting the prediction accuracy to ~50%. |
doi_str_mv | 10.1109/TCSI.2020.3008683 |
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The highly nonlinear subthreshold characteristic of the DA-SCA ensures a strong resilience to machine learning (ML) attacks and it simultaneously achieves low power and compact area. The current difference of two SCAs originated by the manufacturing process is amplified and converted into a voltage difference which is further digitized by the background offset-calibrated oscillator collapse-based comparator. Fabricated in 65 nm CMOS LP technology, the 64-bit DA-SCA PUF shows an average BER of 4.7% in the worst case for the temperature range of −20 to 80° and a supply variation of ±10%. Moreover, the proposed cell-bias-based CRPs filtering method dramatically suppresses the BER to 0.04% while discarding only 9.5% CRPs. The power consumption of the proposed PUF is merely <inline-formula> <tex-math notation="LaTeX">2.4~\mu \text{W} </tex-math></inline-formula> at 125 Kb/s and it occupies 0.024 mm 2 , including the on-chip calibration circuit. The proposed PUF demonstrates resistance against machine learning (ML) attacks across 100K training samples, limiting the prediction accuracy to ~50%.</description><identifier>ISSN: 1549-8328</identifier><identifier>EISSN: 1558-0806</identifier><identifier>DOI: 10.1109/TCSI.2020.3008683</identifier><identifier>CODEN: ITCSCH</identifier><language>eng</language><publisher>New York: IEEE</publisher><subject>Amplification ; authentication ; Bias ; Bit error rate ; Calibration ; Circuits ; CMOS ; Delays ; Filtration ; hardware security ; Internet of Things ; low power ; Machine learning ; machine learning attacks ; Mathematical model ; Physical unclonable function (PUF) ; Power consumption ; Power management ; Resilience ; Subthreshold current ; Transistors</subject><ispartof>IEEE transactions on circuits and systems. I, Regular papers, 2020-11, Vol.67 (11), p.3853-3865</ispartof><rights>Copyright The Institute of Electrical and Electronics Engineers, Inc. (IEEE) 2020</rights><lds50>peer_reviewed</lds50><woscitedreferencessubscribed>false</woscitedreferencessubscribed><citedby>FETCH-LOGICAL-c293t-bb9572f59d1aa4ecaa41e21ed9dd1e81e8a2a09e341369405bd38fb590f48c1f3</citedby><cites>FETCH-LOGICAL-c293t-bb9572f59d1aa4ecaa41e21ed9dd1e81e8a2a09e341369405bd38fb590f48c1f3</cites><orcidid>0000-0003-2821-648X ; 0000-0001-7558-4061 ; 0000-0002-7635-1101 ; 0000-0002-8298-3244</orcidid></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://ieeexplore.ieee.org/document/9144267$$EHTML$$P50$$Gieee$$H</linktohtml><link.rule.ids>314,780,784,796,27924,27925,54758</link.rule.ids><linktorsrc>$$Uhttps://ieeexplore.ieee.org/document/9144267$$EView_record_in_IEEE$$FView_record_in_$$GIEEE</linktorsrc></links><search><creatorcontrib>Liu, Jiahao</creatorcontrib><creatorcontrib>Zhu, Yan</creatorcontrib><creatorcontrib>Chan, Chi-Hang</creatorcontrib><creatorcontrib>Martins, Rui Paulo</creatorcontrib><title>A 0.04% BER Strong PUF With Cell-Bias-Based CRPs Filtering and Background Offset Calibration</title><title>IEEE transactions on circuits and systems. I, Regular papers</title><addtitle>TCSI</addtitle><description>This paper presents a low bit error rate (BER) strong PUF based on the dynamically amplified subthreshold current array (DA-SCA) with cell-bias-based challenge-response-pairs (CRPs) filtering method. The highly nonlinear subthreshold characteristic of the DA-SCA ensures a strong resilience to machine learning (ML) attacks and it simultaneously achieves low power and compact area. The current difference of two SCAs originated by the manufacturing process is amplified and converted into a voltage difference which is further digitized by the background offset-calibrated oscillator collapse-based comparator. Fabricated in 65 nm CMOS LP technology, the 64-bit DA-SCA PUF shows an average BER of 4.7% in the worst case for the temperature range of −20 to 80° and a supply variation of ±10%. Moreover, the proposed cell-bias-based CRPs filtering method dramatically suppresses the BER to 0.04% while discarding only 9.5% CRPs. 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The proposed PUF demonstrates resistance against machine learning (ML) attacks across 100K training samples, limiting the prediction accuracy to ~50%.</description><subject>Amplification</subject><subject>authentication</subject><subject>Bias</subject><subject>Bit error rate</subject><subject>Calibration</subject><subject>Circuits</subject><subject>CMOS</subject><subject>Delays</subject><subject>Filtration</subject><subject>hardware security</subject><subject>Internet of Things</subject><subject>low power</subject><subject>Machine learning</subject><subject>machine learning attacks</subject><subject>Mathematical model</subject><subject>Physical unclonable function (PUF)</subject><subject>Power consumption</subject><subject>Power management</subject><subject>Resilience</subject><subject>Subthreshold current</subject><subject>Transistors</subject><issn>1549-8328</issn><issn>1558-0806</issn><fulltext>true</fulltext><rsrctype>article</rsrctype><creationdate>2020</creationdate><recordtype>article</recordtype><sourceid>RIE</sourceid><recordid>eNo9kE1Lw0AQhhdRsFZ_gHhZEI-Jsx9Jd49taLUgtPQDL8KySXbr1pjU3fTgvzehRRhm3sMzM_AgdE8gJgTk8yZbz2MKFGIGIFLBLtCAJImIQEB62WcuI8GouEY3IewBqARGBuhjjCEG_oQn0xVet76pd3i5neF3137izFRVNHE6RBMdTImz1TLgmata413H6brEE1187Xxz7OLC2mBanOnK5V63rqlv0ZXVVTB35zlE29l0k71Gb4uXeTZ-iwoqWRvluUxG1CayJFpzU3SNGEpMKcuSGNGVphqkYZywVHJI8pIJmycSLBcFsWyIHk93D775OZrQqn1z9HX3UlGepAlNgdCOIieq8E0I3lh18O5b-19FQPUSVS9R9RLVWWK383DaccaYf14Szmk6Yn9VamrX</recordid><startdate>20201101</startdate><enddate>20201101</enddate><creator>Liu, Jiahao</creator><creator>Zhu, Yan</creator><creator>Chan, Chi-Hang</creator><creator>Martins, Rui Paulo</creator><general>IEEE</general><general>The Institute of Electrical and Electronics Engineers, Inc. (IEEE)</general><scope>97E</scope><scope>RIA</scope><scope>RIE</scope><scope>AAYXX</scope><scope>CITATION</scope><scope>7SP</scope><scope>8FD</scope><scope>L7M</scope><orcidid>https://orcid.org/0000-0003-2821-648X</orcidid><orcidid>https://orcid.org/0000-0001-7558-4061</orcidid><orcidid>https://orcid.org/0000-0002-7635-1101</orcidid><orcidid>https://orcid.org/0000-0002-8298-3244</orcidid></search><sort><creationdate>20201101</creationdate><title>A 0.04% BER Strong PUF With Cell-Bias-Based CRPs Filtering and Background Offset Calibration</title><author>Liu, Jiahao ; Zhu, Yan ; Chan, Chi-Hang ; Martins, Rui Paulo</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-c293t-bb9572f59d1aa4ecaa41e21ed9dd1e81e8a2a09e341369405bd38fb590f48c1f3</frbrgroupid><rsrctype>articles</rsrctype><prefilter>articles</prefilter><language>eng</language><creationdate>2020</creationdate><topic>Amplification</topic><topic>authentication</topic><topic>Bias</topic><topic>Bit error rate</topic><topic>Calibration</topic><topic>Circuits</topic><topic>CMOS</topic><topic>Delays</topic><topic>Filtration</topic><topic>hardware security</topic><topic>Internet of Things</topic><topic>low power</topic><topic>Machine learning</topic><topic>machine learning attacks</topic><topic>Mathematical model</topic><topic>Physical unclonable function (PUF)</topic><topic>Power consumption</topic><topic>Power management</topic><topic>Resilience</topic><topic>Subthreshold current</topic><topic>Transistors</topic><toplevel>peer_reviewed</toplevel><toplevel>online_resources</toplevel><creatorcontrib>Liu, Jiahao</creatorcontrib><creatorcontrib>Zhu, Yan</creatorcontrib><creatorcontrib>Chan, Chi-Hang</creatorcontrib><creatorcontrib>Martins, Rui Paulo</creatorcontrib><collection>IEEE All-Society Periodicals Package (ASPP) 2005-present</collection><collection>IEEE All-Society Periodicals Package (ASPP) 1998-Present</collection><collection>IEEE Electronic Library (IEL)</collection><collection>CrossRef</collection><collection>Electronics & Communications Abstracts</collection><collection>Technology Research Database</collection><collection>Advanced Technologies Database with Aerospace</collection><jtitle>IEEE transactions on circuits and systems. I, Regular papers</jtitle></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Liu, Jiahao</au><au>Zhu, Yan</au><au>Chan, Chi-Hang</au><au>Martins, Rui Paulo</au><format>journal</format><genre>article</genre><ristype>JOUR</ristype><atitle>A 0.04% BER Strong PUF With Cell-Bias-Based CRPs Filtering and Background Offset Calibration</atitle><jtitle>IEEE transactions on circuits and systems. I, Regular papers</jtitle><stitle>TCSI</stitle><date>2020-11-01</date><risdate>2020</risdate><volume>67</volume><issue>11</issue><spage>3853</spage><epage>3865</epage><pages>3853-3865</pages><issn>1549-8328</issn><eissn>1558-0806</eissn><coden>ITCSCH</coden><abstract>This paper presents a low bit error rate (BER) strong PUF based on the dynamically amplified subthreshold current array (DA-SCA) with cell-bias-based challenge-response-pairs (CRPs) filtering method. The highly nonlinear subthreshold characteristic of the DA-SCA ensures a strong resilience to machine learning (ML) attacks and it simultaneously achieves low power and compact area. The current difference of two SCAs originated by the manufacturing process is amplified and converted into a voltage difference which is further digitized by the background offset-calibrated oscillator collapse-based comparator. Fabricated in 65 nm CMOS LP technology, the 64-bit DA-SCA PUF shows an average BER of 4.7% in the worst case for the temperature range of −20 to 80° and a supply variation of ±10%. Moreover, the proposed cell-bias-based CRPs filtering method dramatically suppresses the BER to 0.04% while discarding only 9.5% CRPs. The power consumption of the proposed PUF is merely <inline-formula> <tex-math notation="LaTeX">2.4~\mu \text{W} </tex-math></inline-formula> at 125 Kb/s and it occupies 0.024 mm 2 , including the on-chip calibration circuit. The proposed PUF demonstrates resistance against machine learning (ML) attacks across 100K training samples, limiting the prediction accuracy to ~50%.</abstract><cop>New York</cop><pub>IEEE</pub><doi>10.1109/TCSI.2020.3008683</doi><tpages>13</tpages><orcidid>https://orcid.org/0000-0003-2821-648X</orcidid><orcidid>https://orcid.org/0000-0001-7558-4061</orcidid><orcidid>https://orcid.org/0000-0002-7635-1101</orcidid><orcidid>https://orcid.org/0000-0002-8298-3244</orcidid></addata></record> |
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subjects | Amplification authentication Bias Bit error rate Calibration Circuits CMOS Delays Filtration hardware security Internet of Things low power Machine learning machine learning attacks Mathematical model Physical unclonable function (PUF) Power consumption Power management Resilience Subthreshold current Transistors |
title | A 0.04% BER Strong PUF With Cell-Bias-Based CRPs Filtering and Background Offset Calibration |
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