Direct digital frequency synthesizer architecture based on Chebyshev approximation
This paper presents a Chebyshev approximation based method for digital quadrature sine and cosine waveform synthesis. The spurious performance of the Chebyshev approximation is improved by applying the symmetry properties between sine and cosine signals. The frequency synthesizer is modelled with re...
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| creator | Palomaki, K.I. Niittylahti, J. |
| description | This paper presents a Chebyshev approximation based method for digital quadrature sine and cosine waveform synthesis. The spurious performance of the Chebyshev approximation is improved by applying the symmetry properties between sine and cosine signals. The frequency synthesizer is modelled with register transfer level VHDL. Simulation and synthesis results of the Chebyshev sinusoidal signal synthesizer are presented and compared with other direct digital sine and cosine synthesizers. The synthesis is carried out on a 0.35 /spl mu/m, 3.3 V, 4-metal, n-well standard cell process. According to the synthesis results the total design area is 5900 gates and the maximum system clock frequency 160 MHz. |
| doi_str_mv | 10.1109/ACSSC.2000.911267 |
| format | Conference Proceeding |
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The spurious performance of the Chebyshev approximation is improved by applying the symmetry properties between sine and cosine signals. The frequency synthesizer is modelled with register transfer level VHDL. Simulation and synthesis results of the Chebyshev sinusoidal signal synthesizer are presented and compared with other direct digital sine and cosine synthesizers. The synthesis is carried out on a 0.35 /spl mu/m, 3.3 V, 4-metal, n-well standard cell process. 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No.00CH37154)</title><addtitle>ACSSC</addtitle><description>This paper presents a Chebyshev approximation based method for digital quadrature sine and cosine waveform synthesis. The spurious performance of the Chebyshev approximation is improved by applying the symmetry properties between sine and cosine signals. The frequency synthesizer is modelled with register transfer level VHDL. Simulation and synthesis results of the Chebyshev sinusoidal signal synthesizer are presented and compared with other direct digital sine and cosine synthesizers. The synthesis is carried out on a 0.35 /spl mu/m, 3.3 V, 4-metal, n-well standard cell process. According to the synthesis results the total design area is 5900 gates and the maximum system clock frequency 160 MHz.</description><subject>Chebyshev approximation</subject><subject>Clocks</subject><subject>Computer architecture</subject><subject>Equations</subject><subject>Frequency control</subject><subject>Frequency synthesizers</subject><subject>Laboratories</subject><subject>Read only memory</subject><subject>Registers</subject><subject>Signal synthesis</subject><issn>1058-6393</issn><issn>2576-2303</issn><isbn>9780780365148</isbn><isbn>0780365143</isbn><fulltext>true</fulltext><rsrctype>conference_proceeding</rsrctype><creationdate>2000</creationdate><recordtype>conference_proceeding</recordtype><sourceid>6IE</sourceid><sourceid>RIE</sourceid><recordid>eNotUNtKw0AUXLyApfYD9Gl_IHXP3vexxCsUBKvPZZOcNSs1qbupGL_eQIWBeZiZc4Yh5ArYEoC5m1W52ZRLzhhbOgCuzQmZcWV0wQUTp2ThjGUThFYg7RmZAVO20MKJC7LI-WPKMamkYWJGXm5jwnqgTXyPg9_RkPDrgF090jx2Q4s5_mKiPtVtHCbfISGtfMaG9h0tW6zG3OI39ft96n_ipx9i312S8-B3GRf_PCdv93ev5WOxfn54KlfrIoLhQ6GNdzqA4sEjcOldFQxzyno3lQ_GVg2IGniwAmsPUvowKVwzy4XUdaXEnFwf70ZE3O7T9D6N2-Mg4g-IJFNS</recordid><startdate>2000</startdate><enddate>2000</enddate><creator>Palomaki, K.I.</creator><creator>Niittylahti, J.</creator><general>IEEE</general><scope>6IE</scope><scope>6IH</scope><scope>CBEJK</scope><scope>RIE</scope><scope>RIO</scope></search><sort><creationdate>2000</creationdate><title>Direct digital frequency synthesizer architecture based on Chebyshev approximation</title><author>Palomaki, K.I. ; Niittylahti, J.</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-i172t-67a96f152fae124a9bf70958a9807f78bd13c12f83eca144afa9826082346cb53</frbrgroupid><rsrctype>conference_proceedings</rsrctype><prefilter>conference_proceedings</prefilter><language>eng</language><creationdate>2000</creationdate><topic>Chebyshev approximation</topic><topic>Clocks</topic><topic>Computer architecture</topic><topic>Equations</topic><topic>Frequency control</topic><topic>Frequency synthesizers</topic><topic>Laboratories</topic><topic>Read only memory</topic><topic>Registers</topic><topic>Signal synthesis</topic><toplevel>online_resources</toplevel><creatorcontrib>Palomaki, K.I.</creatorcontrib><creatorcontrib>Niittylahti, J.</creatorcontrib><collection>IEEE Electronic Library (IEL) Conference Proceedings</collection><collection>IEEE Proceedings Order Plan (POP) 1998-present by volume</collection><collection>IEEE Xplore All Conference Proceedings</collection><collection>IEEE Electronic Library (IEL)</collection><collection>IEEE Proceedings Order Plans (POP) 1998-present</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Palomaki, K.I.</au><au>Niittylahti, J.</au><format>book</format><genre>proceeding</genre><ristype>CONF</ristype><atitle>Direct digital frequency synthesizer architecture based on Chebyshev approximation</atitle><btitle>Conference Record of the Thirty-Fourth Asilomar Conference on Signals, Systems and Computers (Cat. No.00CH37154)</btitle><stitle>ACSSC</stitle><date>2000</date><risdate>2000</risdate><volume>2</volume><spage>1639</spage><epage>1643 vol.2</epage><pages>1639-1643 vol.2</pages><issn>1058-6393</issn><eissn>2576-2303</eissn><isbn>9780780365148</isbn><isbn>0780365143</isbn><abstract>This paper presents a Chebyshev approximation based method for digital quadrature sine and cosine waveform synthesis. The spurious performance of the Chebyshev approximation is improved by applying the symmetry properties between sine and cosine signals. The frequency synthesizer is modelled with register transfer level VHDL. Simulation and synthesis results of the Chebyshev sinusoidal signal synthesizer are presented and compared with other direct digital sine and cosine synthesizers. The synthesis is carried out on a 0.35 /spl mu/m, 3.3 V, 4-metal, n-well standard cell process. According to the synthesis results the total design area is 5900 gates and the maximum system clock frequency 160 MHz.</abstract><pub>IEEE</pub><doi>10.1109/ACSSC.2000.911267</doi></addata></record> |
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| ispartof | Conference Record of the Thirty-Fourth Asilomar Conference on Signals, Systems and Computers (Cat. No.00CH37154), 2000, Vol.2, p.1639-1643 vol.2 |
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| language | eng |
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| source | IEEE Electronic Library (IEL) Conference Proceedings |
| subjects | Chebyshev approximation Clocks Computer architecture Equations Frequency control Frequency synthesizers Laboratories Read only memory Registers Signal synthesis |
| title | Direct digital frequency synthesizer architecture based on Chebyshev approximation |
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