A Single-Chip Bidirectional Neural Interface With High-Voltage Stimulation and Adaptive Artifact Cancellation in Standard CMOS
A single-chip, bidirectional brain-computer interface (BBCI) enables neuromodulation through simultaneous neural recording and stimulation. This article presents a prototype BBCI application-specified integrated circuit (ASIC) consisting of a 64-channel time-multiplexed recording front-end, an area-...
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| Veröffentlicht in: | IEEE journal of solid-state circuits 2020-07, Vol.55 (7), p.1749-1761 |
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| container_title | IEEE journal of solid-state circuits |
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| creator | Uehlin, John P. Smith, William Anthony Pamula, Venkata Rajesh Pepin, Eric P. Perlmutter, Steve Sathe, Visvesh Rudell, Jacques Christophe |
| description | A single-chip, bidirectional brain-computer interface (BBCI) enables neuromodulation through simultaneous neural recording and stimulation. This article presents a prototype BBCI application-specified integrated circuit (ASIC) consisting of a 64-channel time-multiplexed recording front-end, an area-optimized four-channel high-voltage compliant stimulator, and electronics to support the concurrent multi-channel stimulus artifact cancellation. Stimulator power generation is integrated on a chip, providing ±11-V compliance from low-voltage supplies with a resonant charge pump. High-frequency (~3 GHz) self-resonant clocking is used to reduce the pumping capacitor area while suppressing the associated switching losses. A 32-tap least mean square (LMS)-based digital adaptive filter achieves 60-dB artifact suppression, enabling simultaneous neural stimulation and recording. The entire chip occupies 4 mm 2 in a 65-nm low power (LP) process and is powered by 2.5-/1.2-V supplies, dissipating 205~\mu \text{W} in recording and 142~\mu \text{W} in the stimulation and cancellation back-ends. The stimulation output drivers achieve 31% dc-dc efficiency at a maximum output power of 24 mW. |
| doi_str_mv | 10.1109/JSSC.2020.2991524 |
| format | Article |
| fullrecord | <record><control><sourceid>proquest_RIE</sourceid><recordid>TN_cdi_ieee_primary_9094199</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><ieee_id>9094199</ieee_id><sourcerecordid>2418419706</sourcerecordid><originalsourceid>FETCH-LOGICAL-c384t-103e791c76534c0dca749dbeee1fb06d31ad99ec692bbce9f8a80631afe944063</originalsourceid><addsrcrecordid>eNo9kMtOwzAQRS0EEqXwAYiNJdYpduI8vAwR0KJCF-G1sxxn0rpKk-A4SGz4dhxasZoZ65zR-CJ0ScmMUsJvHvM8m_nEJzOfcxr67AhNaBgmHo2Dj2M0IYQmHvcJOUVnfb91I2MJnaCfFOe6WdfgZRvd4VtdagPK6raRNX6GwbiyaCyYSirA79pu8FyvN95bW1u5BpxbvRtqOQpYNiVOS9lZ_QU4NVY7x-JMNgrqA6IbZzhOmhJnT6v8HJ1Usu7h4lCn6PX-7iWbe8vVwyJLl54KEmY9SgKIOVVxFAZMkVLJmPGyAABaFSQqAypLzkFF3C8KBbxKZEIi91oBZ8x1U3S939uZ9nOA3optOxj3x174jCaM8viPontKmbbvDVSiM3onzbegRIwxizFmMcYsDjE752rvaHfNP88Jdzt58AthGnoG</addsrcrecordid><sourcetype>Aggregation Database</sourcetype><iscdi>true</iscdi><recordtype>article</recordtype><pqid>2418419706</pqid></control><display><type>article</type><title>A Single-Chip Bidirectional Neural Interface With High-Voltage Stimulation and Adaptive Artifact Cancellation in Standard CMOS</title><source>IEEE Electronic Library (IEL)</source><creator>Uehlin, John P. ; Smith, William Anthony ; Pamula, Venkata Rajesh ; Pepin, Eric P. ; Perlmutter, Steve ; Sathe, Visvesh ; Rudell, Jacques Christophe</creator><creatorcontrib>Uehlin, John P. ; Smith, William Anthony ; Pamula, Venkata Rajesh ; Pepin, Eric P. ; Perlmutter, Steve ; Sathe, Visvesh ; Rudell, Jacques Christophe</creatorcontrib><description><![CDATA[A single-chip, bidirectional brain-computer interface (BBCI) enables neuromodulation through simultaneous neural recording and stimulation. This article presents a prototype BBCI application-specified integrated circuit (ASIC) consisting of a 64-channel time-multiplexed recording front-end, an area-optimized four-channel high-voltage compliant stimulator, and electronics to support the concurrent multi-channel stimulus artifact cancellation. Stimulator power generation is integrated on a chip, providing ±11-V compliance from low-voltage supplies with a resonant charge pump. High-frequency (~3 GHz) self-resonant clocking is used to reduce the pumping capacitor area while suppressing the associated switching losses. A 32-tap least mean square (LMS)-based digital adaptive filter achieves 60-dB artifact suppression, enabling simultaneous neural stimulation and recording. The entire chip occupies 4 mm 2 in a 65-nm low power (LP) process and is powered by 2.5-/1.2-V supplies, dissipating <inline-formula> <tex-math notation="LaTeX">205~\mu \text{W} </tex-math></inline-formula> in recording and <inline-formula> <tex-math notation="LaTeX">142~\mu \text{W} </tex-math></inline-formula> in the stimulation and cancellation back-ends. The stimulation output drivers achieve 31% dc-dc efficiency at a maximum output power of 24 mW.]]></description><identifier>ISSN: 0018-9200</identifier><identifier>EISSN: 1558-173X</identifier><identifier>DOI: 10.1109/JSSC.2020.2991524</identifier><identifier>CODEN: IJSCBC</identifier><language>eng</language><publisher>New York: IEEE</publisher><subject>Adaptive filters ; Artifact cancellation ; brain–computer interfaces ; Cancellation ; Capacitors ; Charge pumps ; CMOS ; Electric power generation ; electrical stimulation ; Electrical stimuli ; Electrodes ; High voltages ; Integrated circuits ; neural recording ; Recording ; Resonant frequency ; Stimulation ; Stimulators ; Switches ; time-division multiplexing ; Voltage control</subject><ispartof>IEEE journal of solid-state circuits, 2020-07, Vol.55 (7), p.1749-1761</ispartof><rights>Copyright The Institute of Electrical and Electronics Engineers, Inc. (IEEE) 2020</rights><lds50>peer_reviewed</lds50><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed><citedby>FETCH-LOGICAL-c384t-103e791c76534c0dca749dbeee1fb06d31ad99ec692bbce9f8a80631afe944063</citedby><cites>FETCH-LOGICAL-c384t-103e791c76534c0dca749dbeee1fb06d31ad99ec692bbce9f8a80631afe944063</cites><orcidid>0000-0002-4647-0425 ; 0000-0001-7443-6884 ; 0000-0002-8531-2999 ; 0000-0002-4958-9712</orcidid></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://ieeexplore.ieee.org/document/9094199$$EHTML$$P50$$Gieee$$H</linktohtml><link.rule.ids>314,780,784,796,27924,27925,54758</link.rule.ids><linktorsrc>$$Uhttps://ieeexplore.ieee.org/document/9094199$$EView_record_in_IEEE$$FView_record_in_$$GIEEE</linktorsrc></links><search><creatorcontrib>Uehlin, John P.</creatorcontrib><creatorcontrib>Smith, William Anthony</creatorcontrib><creatorcontrib>Pamula, Venkata Rajesh</creatorcontrib><creatorcontrib>Pepin, Eric P.</creatorcontrib><creatorcontrib>Perlmutter, Steve</creatorcontrib><creatorcontrib>Sathe, Visvesh</creatorcontrib><creatorcontrib>Rudell, Jacques Christophe</creatorcontrib><title>A Single-Chip Bidirectional Neural Interface With High-Voltage Stimulation and Adaptive Artifact Cancellation in Standard CMOS</title><title>IEEE journal of solid-state circuits</title><addtitle>JSSC</addtitle><description><![CDATA[A single-chip, bidirectional brain-computer interface (BBCI) enables neuromodulation through simultaneous neural recording and stimulation. This article presents a prototype BBCI application-specified integrated circuit (ASIC) consisting of a 64-channel time-multiplexed recording front-end, an area-optimized four-channel high-voltage compliant stimulator, and electronics to support the concurrent multi-channel stimulus artifact cancellation. Stimulator power generation is integrated on a chip, providing ±11-V compliance from low-voltage supplies with a resonant charge pump. High-frequency (~3 GHz) self-resonant clocking is used to reduce the pumping capacitor area while suppressing the associated switching losses. A 32-tap least mean square (LMS)-based digital adaptive filter achieves 60-dB artifact suppression, enabling simultaneous neural stimulation and recording. The entire chip occupies 4 mm 2 in a 65-nm low power (LP) process and is powered by 2.5-/1.2-V supplies, dissipating <inline-formula> <tex-math notation="LaTeX">205~\mu \text{W} </tex-math></inline-formula> in recording and <inline-formula> <tex-math notation="LaTeX">142~\mu \text{W} </tex-math></inline-formula> in the stimulation and cancellation back-ends. The stimulation output drivers achieve 31% dc-dc efficiency at a maximum output power of 24 mW.]]></description><subject>Adaptive filters</subject><subject>Artifact cancellation</subject><subject>brain–computer interfaces</subject><subject>Cancellation</subject><subject>Capacitors</subject><subject>Charge pumps</subject><subject>CMOS</subject><subject>Electric power generation</subject><subject>electrical stimulation</subject><subject>Electrical stimuli</subject><subject>Electrodes</subject><subject>High voltages</subject><subject>Integrated circuits</subject><subject>neural recording</subject><subject>Recording</subject><subject>Resonant frequency</subject><subject>Stimulation</subject><subject>Stimulators</subject><subject>Switches</subject><subject>time-division multiplexing</subject><subject>Voltage control</subject><issn>0018-9200</issn><issn>1558-173X</issn><fulltext>true</fulltext><rsrctype>article</rsrctype><creationdate>2020</creationdate><recordtype>article</recordtype><sourceid>RIE</sourceid><recordid>eNo9kMtOwzAQRS0EEqXwAYiNJdYpduI8vAwR0KJCF-G1sxxn0rpKk-A4SGz4dhxasZoZ65zR-CJ0ScmMUsJvHvM8m_nEJzOfcxr67AhNaBgmHo2Dj2M0IYQmHvcJOUVnfb91I2MJnaCfFOe6WdfgZRvd4VtdagPK6raRNX6GwbiyaCyYSirA79pu8FyvN95bW1u5BpxbvRtqOQpYNiVOS9lZ_QU4NVY7x-JMNgrqA6IbZzhOmhJnT6v8HJ1Usu7h4lCn6PX-7iWbe8vVwyJLl54KEmY9SgKIOVVxFAZMkVLJmPGyAABaFSQqAypLzkFF3C8KBbxKZEIi91oBZ8x1U3S939uZ9nOA3optOxj3x174jCaM8viPontKmbbvDVSiM3onzbegRIwxizFmMcYsDjE752rvaHfNP88Jdzt58AthGnoG</recordid><startdate>20200701</startdate><enddate>20200701</enddate><creator>Uehlin, John P.</creator><creator>Smith, William Anthony</creator><creator>Pamula, Venkata Rajesh</creator><creator>Pepin, Eric P.</creator><creator>Perlmutter, Steve</creator><creator>Sathe, Visvesh</creator><creator>Rudell, Jacques Christophe</creator><general>IEEE</general><general>The Institute of Electrical and Electronics Engineers, Inc. (IEEE)</general><scope>97E</scope><scope>RIA</scope><scope>RIE</scope><scope>AAYXX</scope><scope>CITATION</scope><scope>7SP</scope><scope>8FD</scope><scope>L7M</scope><orcidid>https://orcid.org/0000-0002-4647-0425</orcidid><orcidid>https://orcid.org/0000-0001-7443-6884</orcidid><orcidid>https://orcid.org/0000-0002-8531-2999</orcidid><orcidid>https://orcid.org/0000-0002-4958-9712</orcidid></search><sort><creationdate>20200701</creationdate><title>A Single-Chip Bidirectional Neural Interface With High-Voltage Stimulation and Adaptive Artifact Cancellation in Standard CMOS</title><author>Uehlin, John P. ; Smith, William Anthony ; Pamula, Venkata Rajesh ; Pepin, Eric P. ; Perlmutter, Steve ; Sathe, Visvesh ; Rudell, Jacques Christophe</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-c384t-103e791c76534c0dca749dbeee1fb06d31ad99ec692bbce9f8a80631afe944063</frbrgroupid><rsrctype>articles</rsrctype><prefilter>articles</prefilter><language>eng</language><creationdate>2020</creationdate><topic>Adaptive filters</topic><topic>Artifact cancellation</topic><topic>brain–computer interfaces</topic><topic>Cancellation</topic><topic>Capacitors</topic><topic>Charge pumps</topic><topic>CMOS</topic><topic>Electric power generation</topic><topic>electrical stimulation</topic><topic>Electrical stimuli</topic><topic>Electrodes</topic><topic>High voltages</topic><topic>Integrated circuits</topic><topic>neural recording</topic><topic>Recording</topic><topic>Resonant frequency</topic><topic>Stimulation</topic><topic>Stimulators</topic><topic>Switches</topic><topic>time-division multiplexing</topic><topic>Voltage control</topic><toplevel>peer_reviewed</toplevel><toplevel>online_resources</toplevel><creatorcontrib>Uehlin, John P.</creatorcontrib><creatorcontrib>Smith, William Anthony</creatorcontrib><creatorcontrib>Pamula, Venkata Rajesh</creatorcontrib><creatorcontrib>Pepin, Eric P.</creatorcontrib><creatorcontrib>Perlmutter, Steve</creatorcontrib><creatorcontrib>Sathe, Visvesh</creatorcontrib><creatorcontrib>Rudell, Jacques Christophe</creatorcontrib><collection>IEEE All-Society Periodicals Package (ASPP) 2005-present</collection><collection>IEEE All-Society Periodicals Package (ASPP) 1998-Present</collection><collection>IEEE Electronic Library (IEL)</collection><collection>CrossRef</collection><collection>Electronics & Communications Abstracts</collection><collection>Technology Research Database</collection><collection>Advanced Technologies Database with Aerospace</collection><jtitle>IEEE journal of solid-state circuits</jtitle></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Uehlin, John P.</au><au>Smith, William Anthony</au><au>Pamula, Venkata Rajesh</au><au>Pepin, Eric P.</au><au>Perlmutter, Steve</au><au>Sathe, Visvesh</au><au>Rudell, Jacques Christophe</au><format>journal</format><genre>article</genre><ristype>JOUR</ristype><atitle>A Single-Chip Bidirectional Neural Interface With High-Voltage Stimulation and Adaptive Artifact Cancellation in Standard CMOS</atitle><jtitle>IEEE journal of solid-state circuits</jtitle><stitle>JSSC</stitle><date>2020-07-01</date><risdate>2020</risdate><volume>55</volume><issue>7</issue><spage>1749</spage><epage>1761</epage><pages>1749-1761</pages><issn>0018-9200</issn><eissn>1558-173X</eissn><coden>IJSCBC</coden><abstract><![CDATA[A single-chip, bidirectional brain-computer interface (BBCI) enables neuromodulation through simultaneous neural recording and stimulation. This article presents a prototype BBCI application-specified integrated circuit (ASIC) consisting of a 64-channel time-multiplexed recording front-end, an area-optimized four-channel high-voltage compliant stimulator, and electronics to support the concurrent multi-channel stimulus artifact cancellation. Stimulator power generation is integrated on a chip, providing ±11-V compliance from low-voltage supplies with a resonant charge pump. High-frequency (~3 GHz) self-resonant clocking is used to reduce the pumping capacitor area while suppressing the associated switching losses. A 32-tap least mean square (LMS)-based digital adaptive filter achieves 60-dB artifact suppression, enabling simultaneous neural stimulation and recording. The entire chip occupies 4 mm 2 in a 65-nm low power (LP) process and is powered by 2.5-/1.2-V supplies, dissipating <inline-formula> <tex-math notation="LaTeX">205~\mu \text{W} </tex-math></inline-formula> in recording and <inline-formula> <tex-math notation="LaTeX">142~\mu \text{W} </tex-math></inline-formula> in the stimulation and cancellation back-ends. The stimulation output drivers achieve 31% dc-dc efficiency at a maximum output power of 24 mW.]]></abstract><cop>New York</cop><pub>IEEE</pub><doi>10.1109/JSSC.2020.2991524</doi><tpages>13</tpages><orcidid>https://orcid.org/0000-0002-4647-0425</orcidid><orcidid>https://orcid.org/0000-0001-7443-6884</orcidid><orcidid>https://orcid.org/0000-0002-8531-2999</orcidid><orcidid>https://orcid.org/0000-0002-4958-9712</orcidid><oa>free_for_read</oa></addata></record> |
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| subjects | Adaptive filters Artifact cancellation brain–computer interfaces Cancellation Capacitors Charge pumps CMOS Electric power generation electrical stimulation Electrical stimuli Electrodes High voltages Integrated circuits neural recording Recording Resonant frequency Stimulation Stimulators Switches time-division multiplexing Voltage control |
| title | A Single-Chip Bidirectional Neural Interface With High-Voltage Stimulation and Adaptive Artifact Cancellation in Standard CMOS |
| url | https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-01-02T09%3A20%3A00IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-proquest_RIE&rft_val_fmt=info:ofi/fmt:kev:mtx:journal&rft.genre=article&rft.atitle=A%20Single-Chip%20Bidirectional%20Neural%20Interface%20With%20High-Voltage%20Stimulation%20and%20Adaptive%20Artifact%20Cancellation%20in%20Standard%20CMOS&rft.jtitle=IEEE%20journal%20of%20solid-state%20circuits&rft.au=Uehlin,%20John%20P.&rft.date=2020-07-01&rft.volume=55&rft.issue=7&rft.spage=1749&rft.epage=1761&rft.pages=1749-1761&rft.issn=0018-9200&rft.eissn=1558-173X&rft.coden=IJSCBC&rft_id=info:doi/10.1109/JSSC.2020.2991524&rft_dat=%3Cproquest_RIE%3E2418419706%3C/proquest_RIE%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_pqid=2418419706&rft_id=info:pmid/&rft_ieee_id=9094199&rfr_iscdi=true |