Subthreshold Mismatch in Nanometer CMOS at Cryogenic Temperatures
Cryogenic device models are essential for the reliable design of the cryo-CMOS electronic interface necessary to build future large-scale quantum computers. This paper reports the characterization of the drain-current mismatch of NMOS and PMOS devices fabricated in a commercial 40-nm bulk CMOS proce...
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Veröffentlicht in: | IEEE journal of the Electron Devices Society 2020, Vol.8, p.797-806 |
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creator | T Hart, P. A. Babaie, M. Charbon, Edoardo Vladimirescu, Andrei Sebastiano, Fabio |
description | Cryogenic device models are essential for the reliable design of the cryo-CMOS electronic interface necessary to build future large-scale quantum computers. This paper reports the characterization of the drain-current mismatch of NMOS and PMOS devices fabricated in a commercial 40-nm bulk CMOS process over the temperature range from 4.2K to 300 K. By analysing the variability of device parameters over a wide range of device area and length, the validity of the Pelgrom area-scaling law is assessed for the threshold voltage, the current factor and the subthreshold swing. The Croon model is employed to model the drain-current mismatch in moderate to strong inversion, while the weak inversion region is modeled by taking the subthreshold slope variability into account. This results in the first model capable of predicting CMOS-device mismatch over all operating regions and in the whole temperature range from 300K down to 4.2K. |
doi_str_mv | 10.1109/JEDS.2020.2988730 |
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fullrecord | <record><control><sourceid>proquest_ieee_</sourceid><recordid>TN_cdi_ieee_primary_9072133</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><ieee_id>9072133</ieee_id><doaj_id>oai_doaj_org_article_cb17554bb9b949e8aadc128e670d6960</doaj_id><sourcerecordid>2434119421</sourcerecordid><originalsourceid>FETCH-LOGICAL-c402t-456bd0a0ce6adcfad17c5bf2703888209d404314a92c53fa6741c3833e62302f3</originalsourceid><addsrcrecordid>eNpNUEtPwkAQbowmEuQHGC9NPIOzj253jwRRMSAH8LzZbqdQAl3ctgf-vYslxLnMZPI9Zr4oeiQwIgTUy-f0dTWiQGFElZQpg5uoR4mQQ5Eyfvtvvo8Gdb2DUJIIJUQvGq_arNl6rLdun8eLsj6Yxm7jsoq_TOUO2KCPJ4vlKjZNPPEnt8GqtPEaD0f0pmkD8SG6K8y-xsGl96Pvt-l68jGcL99nk_F8aDnQZsgTkeVgwKIwuS1MTlKbZAVNgUkpKaicA2eEG0VtwgojUk4sk4yhoAxowfrRrNPNndnpoy8Pxp-0M6X-Wzi_0cY3pd2jthlJk4RnmcoUVyhNcCRUokghD29D0HrutI7e_bRYN3rnWl-F8zXljBOiOCUBRTqU9a6uPRZXVwL6HLw-B6_PwetL8IHz1HFKRLziFaRBj7FfDyF8kA</addsrcrecordid><sourcetype>Open Website</sourcetype><iscdi>true</iscdi><recordtype>article</recordtype><pqid>2434119421</pqid></control><display><type>article</type><title>Subthreshold Mismatch in Nanometer CMOS at Cryogenic Temperatures</title><source>IEEE Open Access Journals</source><source>DOAJ Directory of Open Access Journals</source><source>EZB-FREE-00999 freely available EZB journals</source><creator>T Hart, P. A. ; Babaie, M. ; Charbon, Edoardo ; Vladimirescu, Andrei ; Sebastiano, Fabio</creator><creatorcontrib>T Hart, P. A. ; Babaie, M. ; Charbon, Edoardo ; Vladimirescu, Andrei ; Sebastiano, Fabio</creatorcontrib><description>Cryogenic device models are essential for the reliable design of the cryo-CMOS electronic interface necessary to build future large-scale quantum computers. This paper reports the characterization of the drain-current mismatch of NMOS and PMOS devices fabricated in a commercial 40-nm bulk CMOS process over the temperature range from 4.2K to 300 K. By analysing the variability of device parameters over a wide range of device area and length, the validity of the Pelgrom area-scaling law is assessed for the threshold voltage, the current factor and the subthreshold swing. The Croon model is employed to model the drain-current mismatch in moderate to strong inversion, while the weak inversion region is modeled by taking the subthreshold slope variability into account. This results in the first model capable of predicting CMOS-device mismatch over all operating regions and in the whole temperature range from 300K down to 4.2K.</description><identifier>ISSN: 2168-6734</identifier><identifier>EISSN: 2168-6734</identifier><identifier>DOI: 10.1109/JEDS.2020.2988730</identifier><identifier>CODEN: IJEDAC</identifier><language>eng</language><publisher>New York: IEEE</publisher><subject>CMOS ; Computer simulation ; Cryogenic temperature ; Cryogenics ; Current measurement ; Geometry ; MOS devices ; Quantum computers ; Scaling laws ; Semiconductor device measurement ; Temperature sensors ; Threshold voltage</subject><ispartof>IEEE journal of the Electron Devices Society, 2020, Vol.8, p.797-806</ispartof><rights>Copyright The Institute of Electrical and Electronics Engineers, Inc. (IEEE) 2020</rights><lds50>peer_reviewed</lds50><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed><citedby>FETCH-LOGICAL-c402t-456bd0a0ce6adcfad17c5bf2703888209d404314a92c53fa6741c3833e62302f3</citedby><cites>FETCH-LOGICAL-c402t-456bd0a0ce6adcfad17c5bf2703888209d404314a92c53fa6741c3833e62302f3</cites><orcidid>0000-0002-0620-3365 ; 0000-0002-8489-9409 ; 0000-0002-4544-855X ; 0000-0001-7635-5324</orcidid></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://ieeexplore.ieee.org/document/9072133$$EHTML$$P50$$Gieee$$Hfree_for_read</linktohtml><link.rule.ids>314,780,784,864,2102,4024,27633,27923,27924,27925,54933</link.rule.ids></links><search><creatorcontrib>T Hart, P. A.</creatorcontrib><creatorcontrib>Babaie, M.</creatorcontrib><creatorcontrib>Charbon, Edoardo</creatorcontrib><creatorcontrib>Vladimirescu, Andrei</creatorcontrib><creatorcontrib>Sebastiano, Fabio</creatorcontrib><title>Subthreshold Mismatch in Nanometer CMOS at Cryogenic Temperatures</title><title>IEEE journal of the Electron Devices Society</title><addtitle>JEDS</addtitle><description>Cryogenic device models are essential for the reliable design of the cryo-CMOS electronic interface necessary to build future large-scale quantum computers. This paper reports the characterization of the drain-current mismatch of NMOS and PMOS devices fabricated in a commercial 40-nm bulk CMOS process over the temperature range from 4.2K to 300 K. By analysing the variability of device parameters over a wide range of device area and length, the validity of the Pelgrom area-scaling law is assessed for the threshold voltage, the current factor and the subthreshold swing. The Croon model is employed to model the drain-current mismatch in moderate to strong inversion, while the weak inversion region is modeled by taking the subthreshold slope variability into account. This results in the first model capable of predicting CMOS-device mismatch over all operating regions and in the whole temperature range from 300K down to 4.2K.</description><subject>CMOS</subject><subject>Computer simulation</subject><subject>Cryogenic temperature</subject><subject>Cryogenics</subject><subject>Current measurement</subject><subject>Geometry</subject><subject>MOS devices</subject><subject>Quantum computers</subject><subject>Scaling laws</subject><subject>Semiconductor device measurement</subject><subject>Temperature sensors</subject><subject>Threshold voltage</subject><issn>2168-6734</issn><issn>2168-6734</issn><fulltext>true</fulltext><rsrctype>article</rsrctype><creationdate>2020</creationdate><recordtype>article</recordtype><sourceid>ESBDL</sourceid><sourceid>RIE</sourceid><sourceid>DOA</sourceid><recordid>eNpNUEtPwkAQbowmEuQHGC9NPIOzj253jwRRMSAH8LzZbqdQAl3ctgf-vYslxLnMZPI9Zr4oeiQwIgTUy-f0dTWiQGFElZQpg5uoR4mQQ5Eyfvtvvo8Gdb2DUJIIJUQvGq_arNl6rLdun8eLsj6Yxm7jsoq_TOUO2KCPJ4vlKjZNPPEnt8GqtPEaD0f0pmkD8SG6K8y-xsGl96Pvt-l68jGcL99nk_F8aDnQZsgTkeVgwKIwuS1MTlKbZAVNgUkpKaicA2eEG0VtwgojUk4sk4yhoAxowfrRrNPNndnpoy8Pxp-0M6X-Wzi_0cY3pd2jthlJk4RnmcoUVyhNcCRUokghD29D0HrutI7e_bRYN3rnWl-F8zXljBOiOCUBRTqU9a6uPRZXVwL6HLw-B6_PwetL8IHz1HFKRLziFaRBj7FfDyF8kA</recordid><startdate>2020</startdate><enddate>2020</enddate><creator>T Hart, P. A.</creator><creator>Babaie, M.</creator><creator>Charbon, Edoardo</creator><creator>Vladimirescu, Andrei</creator><creator>Sebastiano, Fabio</creator><general>IEEE</general><general>The Institute of Electrical and Electronics Engineers, Inc. (IEEE)</general><scope>97E</scope><scope>ESBDL</scope><scope>RIA</scope><scope>RIE</scope><scope>AAYXX</scope><scope>CITATION</scope><scope>7SP</scope><scope>8FD</scope><scope>L7M</scope><scope>DOA</scope><orcidid>https://orcid.org/0000-0002-0620-3365</orcidid><orcidid>https://orcid.org/0000-0002-8489-9409</orcidid><orcidid>https://orcid.org/0000-0002-4544-855X</orcidid><orcidid>https://orcid.org/0000-0001-7635-5324</orcidid></search><sort><creationdate>2020</creationdate><title>Subthreshold Mismatch in Nanometer CMOS at Cryogenic Temperatures</title><author>T Hart, P. A. ; Babaie, M. ; Charbon, Edoardo ; Vladimirescu, Andrei ; Sebastiano, Fabio</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-c402t-456bd0a0ce6adcfad17c5bf2703888209d404314a92c53fa6741c3833e62302f3</frbrgroupid><rsrctype>articles</rsrctype><prefilter>articles</prefilter><language>eng</language><creationdate>2020</creationdate><topic>CMOS</topic><topic>Computer simulation</topic><topic>Cryogenic temperature</topic><topic>Cryogenics</topic><topic>Current measurement</topic><topic>Geometry</topic><topic>MOS devices</topic><topic>Quantum computers</topic><topic>Scaling laws</topic><topic>Semiconductor device measurement</topic><topic>Temperature sensors</topic><topic>Threshold voltage</topic><toplevel>peer_reviewed</toplevel><toplevel>online_resources</toplevel><creatorcontrib>T Hart, P. A.</creatorcontrib><creatorcontrib>Babaie, M.</creatorcontrib><creatorcontrib>Charbon, Edoardo</creatorcontrib><creatorcontrib>Vladimirescu, Andrei</creatorcontrib><creatorcontrib>Sebastiano, Fabio</creatorcontrib><collection>IEEE All-Society Periodicals Package (ASPP) 2005-present</collection><collection>IEEE Open Access Journals</collection><collection>IEEE All-Society Periodicals Package (ASPP) 1998-Present</collection><collection>IEEE Electronic Library (IEL)</collection><collection>CrossRef</collection><collection>Electronics & Communications Abstracts</collection><collection>Technology Research Database</collection><collection>Advanced Technologies Database with Aerospace</collection><collection>DOAJ Directory of Open Access Journals</collection><jtitle>IEEE journal of the Electron Devices Society</jtitle></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext</fulltext></delivery><addata><au>T Hart, P. A.</au><au>Babaie, M.</au><au>Charbon, Edoardo</au><au>Vladimirescu, Andrei</au><au>Sebastiano, Fabio</au><format>journal</format><genre>article</genre><ristype>JOUR</ristype><atitle>Subthreshold Mismatch in Nanometer CMOS at Cryogenic Temperatures</atitle><jtitle>IEEE journal of the Electron Devices Society</jtitle><stitle>JEDS</stitle><date>2020</date><risdate>2020</risdate><volume>8</volume><spage>797</spage><epage>806</epage><pages>797-806</pages><issn>2168-6734</issn><eissn>2168-6734</eissn><coden>IJEDAC</coden><abstract>Cryogenic device models are essential for the reliable design of the cryo-CMOS electronic interface necessary to build future large-scale quantum computers. This paper reports the characterization of the drain-current mismatch of NMOS and PMOS devices fabricated in a commercial 40-nm bulk CMOS process over the temperature range from 4.2K to 300 K. By analysing the variability of device parameters over a wide range of device area and length, the validity of the Pelgrom area-scaling law is assessed for the threshold voltage, the current factor and the subthreshold swing. The Croon model is employed to model the drain-current mismatch in moderate to strong inversion, while the weak inversion region is modeled by taking the subthreshold slope variability into account. This results in the first model capable of predicting CMOS-device mismatch over all operating regions and in the whole temperature range from 300K down to 4.2K.</abstract><cop>New York</cop><pub>IEEE</pub><doi>10.1109/JEDS.2020.2988730</doi><tpages>10</tpages><orcidid>https://orcid.org/0000-0002-0620-3365</orcidid><orcidid>https://orcid.org/0000-0002-8489-9409</orcidid><orcidid>https://orcid.org/0000-0002-4544-855X</orcidid><orcidid>https://orcid.org/0000-0001-7635-5324</orcidid><oa>free_for_read</oa></addata></record> |
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subjects | CMOS Computer simulation Cryogenic temperature Cryogenics Current measurement Geometry MOS devices Quantum computers Scaling laws Semiconductor device measurement Temperature sensors Threshold voltage |
title | Subthreshold Mismatch in Nanometer CMOS at Cryogenic Temperatures |
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