A Framed-Pulsewidth Modulation Transceiver for High-Speed Broadband Communication Links
A 20 Gb/s serial link transceiver employing a framed-pulsewidth modulation (FPWM) scheme that overcomes the signal-to-noise (SNR) degradation without a linearity requirement is presented. The FPWM scheme encodes data at the location and the width of the pulses in a frame spanning multiple unit inter...
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| Veröffentlicht in: | IEEE transactions on circuits and systems. I, Regular papers Regular papers, 2020-08, Vol.67 (8), p.2825-2835 |
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| container_title | IEEE transactions on circuits and systems. I, Regular papers |
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| creator | Jeon, Sejun Kwon, Woohyun Yoon, Jong-Hyeok Yoon, Taehun Kwon, Kyeongha Yang, Jaehyeok Bae, Hyeon-Min |
| description | A 20 Gb/s serial link transceiver employing a framed-pulsewidth modulation (FPWM) scheme that overcomes the signal-to-noise (SNR) degradation without a linearity requirement is presented. The FPWM scheme encodes data at the location and the width of the pulses in a frame spanning multiple unit intervals (UI) while maintaining a minimum pulsewidth equal to 1 UI. The test chip achieves a coding gain of 33 %, which allows a total throughput of 20 Gb/s while keeping the baud rate of 15 Gb/s. The equalization core incorporating programmable 3-tap pre-emphasis at the transmitter and a continuous-time linear equalizer (CTLE) at the receiver compensates for the channel insertion loss up to 12 dB at the baud frequency, and achieves < 10 −12 of bit error rate (BER). The transceiver IC, fabricated in 40 nm CMOS, occupies 2.2\times0.48 mm 2 and consumes 90.6 mW from a 0.9 V supply which renders the power efficiency of 4.53 mW/Gb/s. |
| doi_str_mv | 10.1109/TCSI.2020.2982050 |
| format | Article |
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The FPWM scheme encodes data at the location and the width of the pulses in a frame spanning multiple unit intervals (UI) while maintaining a minimum pulsewidth equal to 1 UI. The test chip achieves a coding gain of 33 %, which allows a total throughput of 20 Gb/s while keeping the baud rate of 15 Gb/s. The equalization core incorporating programmable 3-tap pre-emphasis at the transmitter and a continuous-time linear equalizer (CTLE) at the receiver compensates for the channel insertion loss up to 12 dB at the baud frequency, and achieves < 10 −12 of bit error rate (BER). The transceiver IC, fabricated in 40 nm CMOS, occupies <inline-formula> <tex-math notation="LaTeX">2.2\times0.48 </tex-math></inline-formula> mm 2 and consumes 90.6 mW from a 0.9 V supply which renders the power efficiency of 4.53 mW/Gb/s.</description><identifier>ISSN: 1549-8328</identifier><identifier>EISSN: 1558-0806</identifier><identifier>DOI: 10.1109/TCSI.2020.2982050</identifier><identifier>CODEN: ITCSCH</identifier><language>eng</language><publisher>New York: IEEE</publisher><subject>Boosting ; Broadband ; clock and data recovery (CDR) ; decoder ; Degradation ; encoder ; Encoding ; Equalization ; frame ; I/O ; Insertion loss ; interconnect ; Linearity ; Modulation ; serdes ; serial link ; Signal to noise ratio ; spectral efficiency ; Time-domain analysis ; transceiver ; Transceivers ; wireline</subject><ispartof>IEEE transactions on circuits and systems. I, Regular papers, 2020-08, Vol.67 (8), p.2825-2835</ispartof><rights>Copyright The Institute of Electrical and Electronics Engineers, Inc. (IEEE) 2020</rights><lds50>peer_reviewed</lds50><woscitedreferencessubscribed>false</woscitedreferencessubscribed><citedby>FETCH-LOGICAL-c359t-d9e1d8affbb8fb97c6877f382847a6ab9e66520b5ed4f41b46162369b22bb593</citedby><cites>FETCH-LOGICAL-c359t-d9e1d8affbb8fb97c6877f382847a6ab9e66520b5ed4f41b46162369b22bb593</cites><orcidid>0000-0002-2373-7799 ; 0000-0002-5728-6711 ; 0000-0001-5513-5285 ; 0000-0001-7373-7028 ; 0000-0003-0199-3756</orcidid></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://ieeexplore.ieee.org/document/9057372$$EHTML$$P50$$Gieee$$H</linktohtml><link.rule.ids>315,781,785,797,27926,27927,54760</link.rule.ids><linktorsrc>$$Uhttps://ieeexplore.ieee.org/document/9057372$$EView_record_in_IEEE$$FView_record_in_$$GIEEE</linktorsrc></links><search><creatorcontrib>Jeon, Sejun</creatorcontrib><creatorcontrib>Kwon, Woohyun</creatorcontrib><creatorcontrib>Yoon, Jong-Hyeok</creatorcontrib><creatorcontrib>Yoon, Taehun</creatorcontrib><creatorcontrib>Kwon, Kyeongha</creatorcontrib><creatorcontrib>Yang, Jaehyeok</creatorcontrib><creatorcontrib>Bae, Hyeon-Min</creatorcontrib><title>A Framed-Pulsewidth Modulation Transceiver for High-Speed Broadband Communication Links</title><title>IEEE transactions on circuits and systems. I, Regular papers</title><addtitle>TCSI</addtitle><description>A 20 Gb/s serial link transceiver employing a framed-pulsewidth modulation (FPWM) scheme that overcomes the signal-to-noise (SNR) degradation without a linearity requirement is presented. The FPWM scheme encodes data at the location and the width of the pulses in a frame spanning multiple unit intervals (UI) while maintaining a minimum pulsewidth equal to 1 UI. The test chip achieves a coding gain of 33 %, which allows a total throughput of 20 Gb/s while keeping the baud rate of 15 Gb/s. The equalization core incorporating programmable 3-tap pre-emphasis at the transmitter and a continuous-time linear equalizer (CTLE) at the receiver compensates for the channel insertion loss up to 12 dB at the baud frequency, and achieves < 10 −12 of bit error rate (BER). The transceiver IC, fabricated in 40 nm CMOS, occupies <inline-formula> <tex-math notation="LaTeX">2.2\times0.48 </tex-math></inline-formula> mm 2 and consumes 90.6 mW from a 0.9 V supply which renders the power efficiency of 4.53 mW/Gb/s.</description><subject>Boosting</subject><subject>Broadband</subject><subject>clock and data recovery (CDR)</subject><subject>decoder</subject><subject>Degradation</subject><subject>encoder</subject><subject>Encoding</subject><subject>Equalization</subject><subject>frame</subject><subject>I/O</subject><subject>Insertion loss</subject><subject>interconnect</subject><subject>Linearity</subject><subject>Modulation</subject><subject>serdes</subject><subject>serial link</subject><subject>Signal to noise ratio</subject><subject>spectral efficiency</subject><subject>Time-domain analysis</subject><subject>transceiver</subject><subject>Transceivers</subject><subject>wireline</subject><issn>1549-8328</issn><issn>1558-0806</issn><fulltext>true</fulltext><rsrctype>article</rsrctype><creationdate>2020</creationdate><recordtype>article</recordtype><sourceid>RIE</sourceid><recordid>eNo9kF1LwzAYhYMoOKc_QLwpeN2ZjyZNLmdxbjBRWMHLkDSJy1zbmayK_96WDq_ec_Gc88IDwC2CM4SgeCiLzWqGIYYzLDiGFJ6BCaKUp5BDdj7kTKScYH4JrmLcQYgFJGgC3ufJIqjamvSt20f7481xm7y0pturo2-bpAyqiZX13zYkrg3J0n9s083BWpM8hlYZrRqTFG1dd42vxsraN5_xGlw41Q_enO4UlIunslim69fnVTFfpxWh4pgaYZHhyjmtudMirxjPc0c45lmumNLCMkYx1NSazGVIZwwxTJjQGGtNBZmC-3H2ENqvzsaj3LVdaPqPEmdY4B7PWU-hkapCG2OwTh6Cr1X4lQjKQZ8c9MlBnzzp6zt3Y8dba_95AWlOckz-AC2ca8E</recordid><startdate>20200801</startdate><enddate>20200801</enddate><creator>Jeon, Sejun</creator><creator>Kwon, Woohyun</creator><creator>Yoon, Jong-Hyeok</creator><creator>Yoon, Taehun</creator><creator>Kwon, Kyeongha</creator><creator>Yang, Jaehyeok</creator><creator>Bae, Hyeon-Min</creator><general>IEEE</general><general>The Institute of Electrical and Electronics Engineers, Inc. (IEEE)</general><scope>97E</scope><scope>RIA</scope><scope>RIE</scope><scope>AAYXX</scope><scope>CITATION</scope><scope>7SP</scope><scope>8FD</scope><scope>L7M</scope><orcidid>https://orcid.org/0000-0002-2373-7799</orcidid><orcidid>https://orcid.org/0000-0002-5728-6711</orcidid><orcidid>https://orcid.org/0000-0001-5513-5285</orcidid><orcidid>https://orcid.org/0000-0001-7373-7028</orcidid><orcidid>https://orcid.org/0000-0003-0199-3756</orcidid></search><sort><creationdate>20200801</creationdate><title>A Framed-Pulsewidth Modulation Transceiver for High-Speed Broadband Communication Links</title><author>Jeon, Sejun ; Kwon, Woohyun ; Yoon, Jong-Hyeok ; Yoon, Taehun ; Kwon, Kyeongha ; Yang, Jaehyeok ; Bae, Hyeon-Min</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-c359t-d9e1d8affbb8fb97c6877f382847a6ab9e66520b5ed4f41b46162369b22bb593</frbrgroupid><rsrctype>articles</rsrctype><prefilter>articles</prefilter><language>eng</language><creationdate>2020</creationdate><topic>Boosting</topic><topic>Broadband</topic><topic>clock and data recovery (CDR)</topic><topic>decoder</topic><topic>Degradation</topic><topic>encoder</topic><topic>Encoding</topic><topic>Equalization</topic><topic>frame</topic><topic>I/O</topic><topic>Insertion loss</topic><topic>interconnect</topic><topic>Linearity</topic><topic>Modulation</topic><topic>serdes</topic><topic>serial link</topic><topic>Signal to noise ratio</topic><topic>spectral efficiency</topic><topic>Time-domain analysis</topic><topic>transceiver</topic><topic>Transceivers</topic><topic>wireline</topic><toplevel>peer_reviewed</toplevel><toplevel>online_resources</toplevel><creatorcontrib>Jeon, Sejun</creatorcontrib><creatorcontrib>Kwon, Woohyun</creatorcontrib><creatorcontrib>Yoon, Jong-Hyeok</creatorcontrib><creatorcontrib>Yoon, Taehun</creatorcontrib><creatorcontrib>Kwon, Kyeongha</creatorcontrib><creatorcontrib>Yang, Jaehyeok</creatorcontrib><creatorcontrib>Bae, Hyeon-Min</creatorcontrib><collection>IEEE All-Society Periodicals Package (ASPP) 2005-present</collection><collection>IEEE All-Society Periodicals Package (ASPP) 1998-Present</collection><collection>IEEE Electronic Library (IEL)</collection><collection>CrossRef</collection><collection>Electronics & Communications Abstracts</collection><collection>Technology Research Database</collection><collection>Advanced Technologies Database with Aerospace</collection><jtitle>IEEE transactions on circuits and systems. I, Regular papers</jtitle></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Jeon, Sejun</au><au>Kwon, Woohyun</au><au>Yoon, Jong-Hyeok</au><au>Yoon, Taehun</au><au>Kwon, Kyeongha</au><au>Yang, Jaehyeok</au><au>Bae, Hyeon-Min</au><format>journal</format><genre>article</genre><ristype>JOUR</ristype><atitle>A Framed-Pulsewidth Modulation Transceiver for High-Speed Broadband Communication Links</atitle><jtitle>IEEE transactions on circuits and systems. I, Regular papers</jtitle><stitle>TCSI</stitle><date>2020-08-01</date><risdate>2020</risdate><volume>67</volume><issue>8</issue><spage>2825</spage><epage>2835</epage><pages>2825-2835</pages><issn>1549-8328</issn><eissn>1558-0806</eissn><coden>ITCSCH</coden><abstract>A 20 Gb/s serial link transceiver employing a framed-pulsewidth modulation (FPWM) scheme that overcomes the signal-to-noise (SNR) degradation without a linearity requirement is presented. The FPWM scheme encodes data at the location and the width of the pulses in a frame spanning multiple unit intervals (UI) while maintaining a minimum pulsewidth equal to 1 UI. The test chip achieves a coding gain of 33 %, which allows a total throughput of 20 Gb/s while keeping the baud rate of 15 Gb/s. The equalization core incorporating programmable 3-tap pre-emphasis at the transmitter and a continuous-time linear equalizer (CTLE) at the receiver compensates for the channel insertion loss up to 12 dB at the baud frequency, and achieves < 10 −12 of bit error rate (BER). The transceiver IC, fabricated in 40 nm CMOS, occupies <inline-formula> <tex-math notation="LaTeX">2.2\times0.48 </tex-math></inline-formula> mm 2 and consumes 90.6 mW from a 0.9 V supply which renders the power efficiency of 4.53 mW/Gb/s.</abstract><cop>New York</cop><pub>IEEE</pub><doi>10.1109/TCSI.2020.2982050</doi><tpages>11</tpages><orcidid>https://orcid.org/0000-0002-2373-7799</orcidid><orcidid>https://orcid.org/0000-0002-5728-6711</orcidid><orcidid>https://orcid.org/0000-0001-5513-5285</orcidid><orcidid>https://orcid.org/0000-0001-7373-7028</orcidid><orcidid>https://orcid.org/0000-0003-0199-3756</orcidid></addata></record> |
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| subjects | Boosting Broadband clock and data recovery (CDR) decoder Degradation encoder Encoding Equalization frame I/O Insertion loss interconnect Linearity Modulation serdes serial link Signal to noise ratio spectral efficiency Time-domain analysis transceiver Transceivers wireline |
| title | A Framed-Pulsewidth Modulation Transceiver for High-Speed Broadband Communication Links |
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