A Framed-Pulsewidth Modulation Transceiver for High-Speed Broadband Communication Links

A 20 Gb/s serial link transceiver employing a framed-pulsewidth modulation (FPWM) scheme that overcomes the signal-to-noise (SNR) degradation without a linearity requirement is presented. The FPWM scheme encodes data at the location and the width of the pulses in a frame spanning multiple unit intervals (UI) while maintaining a minimum pulsewidth equal to 1 UI. The test chip achieves a coding gain of 33 %, which allows a total throughput of 20 Gb/s while keeping the baud rate of 15 Gb/s. The equalization core incorporating programmable 3-tap pre-emphasis at the transmitter and a continuous-time linear equalizer (CTLE) at the receiver compensates for the channel insertion loss up to 12 dB at the baud frequency, and achieves < 10 −12 of bit error rate (BER). The transceiver IC, fabricated in 40 nm CMOS, occupies 2.2\times0.48 mm 2 and consumes 90.6 mW from a 0.9 V supply which renders the power efficiency of 4.53 mW/Gb/s.