Defect Analysis and Parallel Testing for 3D Hybrid CMOS-Memristor Memory
CMOS Molecular (CMOL) architecture, which can alleviate the sneak path problem of one memristor (1R) crossbars and limit its power consumption, can be used in a large-scale memory system. In this article, we analyze the electrical defects in a CMOL circuit including open and bridge. A parallel March...
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| Veröffentlicht in: | IEEE transactions on emerging topics in computing 2021-04, Vol.9 (2), p.745-758 |
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| creator | Liu, Peng You, Zhiqiang Wu, Jigang Elimu, Michael Wang, Weizheng Cai, Shuo Han, Yinhe |
| description | CMOS Molecular (CMOL) architecture, which can alleviate the sneak path problem of one memristor (1R) crossbars and limit its power consumption, can be used in a large-scale memory system. In this article, we analyze the electrical defects in a CMOL circuit including open and bridge. A parallel March-like test algorithm is presented for the CMOL architecture, which covers the faults caused by the open and bridge defects and parametric variations during its fabrication. Analysis results show that the test time of the proposed test algorithm is reduced significantly compared with the enhanced methods of March-MOM and March C* for CMOL architectures. The write time is reduced approximately 5n/4\times 5n/4× and n\times n× , respectively, where n n is the number of memristors attached to a nanowire segment. The read time is also reduced drastically. Finally, a design for testability (DFT) architecture is proposed to adapt the parallel March-like test algorithm. In compare with the short write time testing scheme, the proposed DFT can achieve 35.4 percent of reduction in area overhead, with 14.52 percent more power overhead kept the same delay in a CMOL circuit with 64 memory cells. |
| doi_str_mv | 10.1109/TETC.2020.2982830 |
| format | Article |
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In this article, we analyze the electrical defects in a CMOL circuit including open and bridge. A parallel March-like test algorithm is presented for the CMOL architecture, which covers the faults caused by the open and bridge defects and parametric variations during its fabrication. Analysis results show that the test time of the proposed test algorithm is reduced significantly compared with the enhanced methods of March-MOM and March C* for CMOL architectures. The write time is reduced approximately <inline-formula><tex-math notation="LaTeX">5n/4\times</tex-math> <mml:math><mml:mrow><mml:mn>5</mml:mn><mml:mi>n</mml:mi><mml:mo>/</mml:mo><mml:mn>4</mml:mn><mml:mo>×</mml:mo></mml:mrow></mml:math><inline-graphic xlink:href="liu-ieq1-2982830.gif"/> </inline-formula> and <inline-formula><tex-math notation="LaTeX">n\times</tex-math> <mml:math><mml:mrow><mml:mi>n</mml:mi><mml:mo>×</mml:mo></mml:mrow></mml:math><inline-graphic xlink:href="liu-ieq2-2982830.gif"/> </inline-formula>, respectively, where <inline-formula><tex-math notation="LaTeX">n</tex-math> <mml:math><mml:mi>n</mml:mi></mml:math><inline-graphic xlink:href="liu-ieq3-2982830.gif"/> </inline-formula> is the number of memristors attached to a nanowire segment. The read time is also reduced drastically. Finally, a design for testability (DFT) architecture is proposed to adapt the parallel March-like test algorithm. In compare with the short write time testing scheme, the proposed DFT can achieve 35.4 percent of reduction in area overhead, with 14.52 percent more power overhead kept the same delay in a CMOL circuit with 64 memory cells.]]></description><identifier>ISSN: 2168-6750</identifier><identifier>EISSN: 2168-6750</identifier><identifier>DOI: 10.1109/TETC.2020.2982830</identifier><identifier>CODEN: ITETBT</identifier><language>eng</language><publisher>New York: IEEE</publisher><subject>Algorithms ; Circuit faults ; Circuits ; CMOL ; CMOS ; Computer architecture ; Computer memory ; Defects ; Discrete Fourier transforms ; memristor ; Memristors ; Nanowires ; Non-volatile memory ; Power consumption ; Random access memory ; Resistance ; RRAM ; Testability ; Testing ; Testing time</subject><ispartof>IEEE transactions on emerging topics in computing, 2021-04, Vol.9 (2), p.745-758</ispartof><rights>Copyright The Institute of Electrical and Electronics Engineers, Inc. (IEEE) 2021</rights><lds50>peer_reviewed</lds50><woscitedreferencessubscribed>false</woscitedreferencessubscribed><citedby>FETCH-LOGICAL-c293t-f16ba0daebd504434b8bb349e5550cd4e7e72c7f484602bd6a1e15fb04c51c353</citedby><cites>FETCH-LOGICAL-c293t-f16ba0daebd504434b8bb349e5550cd4e7e72c7f484602bd6a1e15fb04c51c353</cites><orcidid>0000-0003-4375-3187 ; 0000-0002-2329-502X ; 0000-0002-6470-9794 ; 0000-0001-9924-0685 ; 0000-0003-0904-6681</orcidid></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://ieeexplore.ieee.org/document/9052438$$EHTML$$P50$$Gieee$$H</linktohtml><link.rule.ids>314,780,784,796,27631,27922,27923,54756,54931</link.rule.ids><linktorsrc>$$Uhttps://ieeexplore.ieee.org/document/9052438$$EView_record_in_IEEE$$FView_record_in_$$GIEEE</linktorsrc></links><search><creatorcontrib>Liu, Peng</creatorcontrib><creatorcontrib>You, Zhiqiang</creatorcontrib><creatorcontrib>Wu, Jigang</creatorcontrib><creatorcontrib>Elimu, Michael</creatorcontrib><creatorcontrib>Wang, Weizheng</creatorcontrib><creatorcontrib>Cai, Shuo</creatorcontrib><creatorcontrib>Han, Yinhe</creatorcontrib><title>Defect Analysis and Parallel Testing for 3D Hybrid CMOS-Memristor Memory</title><title>IEEE transactions on emerging topics in computing</title><addtitle>TETC</addtitle><description><![CDATA[CMOS Molecular (CMOL) architecture, which can alleviate the sneak path problem of one memristor (1R) crossbars and limit its power consumption, can be used in a large-scale memory system. In this article, we analyze the electrical defects in a CMOL circuit including open and bridge. A parallel March-like test algorithm is presented for the CMOL architecture, which covers the faults caused by the open and bridge defects and parametric variations during its fabrication. Analysis results show that the test time of the proposed test algorithm is reduced significantly compared with the enhanced methods of March-MOM and March C* for CMOL architectures. The write time is reduced approximately <inline-formula><tex-math notation="LaTeX">5n/4\times</tex-math> <mml:math><mml:mrow><mml:mn>5</mml:mn><mml:mi>n</mml:mi><mml:mo>/</mml:mo><mml:mn>4</mml:mn><mml:mo>×</mml:mo></mml:mrow></mml:math><inline-graphic xlink:href="liu-ieq1-2982830.gif"/> </inline-formula> and <inline-formula><tex-math notation="LaTeX">n\times</tex-math> <mml:math><mml:mrow><mml:mi>n</mml:mi><mml:mo>×</mml:mo></mml:mrow></mml:math><inline-graphic xlink:href="liu-ieq2-2982830.gif"/> </inline-formula>, respectively, where <inline-formula><tex-math notation="LaTeX">n</tex-math> <mml:math><mml:mi>n</mml:mi></mml:math><inline-graphic xlink:href="liu-ieq3-2982830.gif"/> </inline-formula> is the number of memristors attached to a nanowire segment. The read time is also reduced drastically. Finally, a design for testability (DFT) architecture is proposed to adapt the parallel March-like test algorithm. In compare with the short write time testing scheme, the proposed DFT can achieve 35.4 percent of reduction in area overhead, with 14.52 percent more power overhead kept the same delay in a CMOL circuit with 64 memory cells.]]></description><subject>Algorithms</subject><subject>Circuit faults</subject><subject>Circuits</subject><subject>CMOL</subject><subject>CMOS</subject><subject>Computer architecture</subject><subject>Computer memory</subject><subject>Defects</subject><subject>Discrete Fourier transforms</subject><subject>memristor</subject><subject>Memristors</subject><subject>Nanowires</subject><subject>Non-volatile memory</subject><subject>Power consumption</subject><subject>Random access memory</subject><subject>Resistance</subject><subject>RRAM</subject><subject>Testability</subject><subject>Testing</subject><subject>Testing time</subject><issn>2168-6750</issn><issn>2168-6750</issn><fulltext>true</fulltext><rsrctype>article</rsrctype><creationdate>2021</creationdate><recordtype>article</recordtype><sourceid>RIE</sourceid><recordid>eNpNkE9LAzEQxYMoWLQfQLwEPG_N_80eS6tWaKlgPYckO5Et225Ntof99qa0iHOZB_Pe8Pgh9EDJhFJSPW9eNrMJI4xMWKWZ5uQKjRhVulClJNf_9C0ap7QleTRVlSpHaDGHAL7H071th9QkbPc1_rDRti20eAOpb_bfOHQR8zleDC42NZ6t1p_FCnaxSX0-ZNXF4R7dBNsmGF_2Hfp6zbUWxXL99j6bLgvPKt4XgSpnSW3B1ZIIwYXTznFRgZSS-FpACSXzZRBaKMJcrSwFKoMjwkvqueR36On89xC7n2PuZ7bdMeb2yTDJlVZSMpVd9OzysUspQjCH2OxsHAwl5sTMnJiZEzNzYZYzj-dMAwB__opIJrjmvxm-ZiE</recordid><startdate>20210401</startdate><enddate>20210401</enddate><creator>Liu, Peng</creator><creator>You, Zhiqiang</creator><creator>Wu, Jigang</creator><creator>Elimu, Michael</creator><creator>Wang, Weizheng</creator><creator>Cai, Shuo</creator><creator>Han, Yinhe</creator><general>IEEE</general><general>The Institute of Electrical and Electronics Engineers, Inc. (IEEE)</general><scope>97E</scope><scope>RIA</scope><scope>RIE</scope><scope>AAYXX</scope><scope>CITATION</scope><scope>7SC</scope><scope>8FD</scope><scope>JQ2</scope><scope>L7M</scope><scope>L~C</scope><scope>L~D</scope><orcidid>https://orcid.org/0000-0003-4375-3187</orcidid><orcidid>https://orcid.org/0000-0002-2329-502X</orcidid><orcidid>https://orcid.org/0000-0002-6470-9794</orcidid><orcidid>https://orcid.org/0000-0001-9924-0685</orcidid><orcidid>https://orcid.org/0000-0003-0904-6681</orcidid></search><sort><creationdate>20210401</creationdate><title>Defect Analysis and Parallel Testing for 3D Hybrid CMOS-Memristor Memory</title><author>Liu, Peng ; You, Zhiqiang ; Wu, Jigang ; Elimu, Michael ; Wang, Weizheng ; Cai, Shuo ; Han, Yinhe</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-c293t-f16ba0daebd504434b8bb349e5550cd4e7e72c7f484602bd6a1e15fb04c51c353</frbrgroupid><rsrctype>articles</rsrctype><prefilter>articles</prefilter><language>eng</language><creationdate>2021</creationdate><topic>Algorithms</topic><topic>Circuit faults</topic><topic>Circuits</topic><topic>CMOL</topic><topic>CMOS</topic><topic>Computer architecture</topic><topic>Computer memory</topic><topic>Defects</topic><topic>Discrete Fourier transforms</topic><topic>memristor</topic><topic>Memristors</topic><topic>Nanowires</topic><topic>Non-volatile memory</topic><topic>Power consumption</topic><topic>Random access memory</topic><topic>Resistance</topic><topic>RRAM</topic><topic>Testability</topic><topic>Testing</topic><topic>Testing time</topic><toplevel>peer_reviewed</toplevel><toplevel>online_resources</toplevel><creatorcontrib>Liu, Peng</creatorcontrib><creatorcontrib>You, Zhiqiang</creatorcontrib><creatorcontrib>Wu, Jigang</creatorcontrib><creatorcontrib>Elimu, Michael</creatorcontrib><creatorcontrib>Wang, Weizheng</creatorcontrib><creatorcontrib>Cai, Shuo</creatorcontrib><creatorcontrib>Han, Yinhe</creatorcontrib><collection>IEEE All-Society Periodicals Package (ASPP) 2005-present</collection><collection>IEEE All-Society Periodicals Package (ASPP) 1998-Present</collection><collection>IEEE Electronic Library (IEL)</collection><collection>CrossRef</collection><collection>Computer and Information Systems Abstracts</collection><collection>Technology Research Database</collection><collection>ProQuest Computer Science Collection</collection><collection>Advanced Technologies Database with Aerospace</collection><collection>Computer and Information Systems Abstracts Academic</collection><collection>Computer and Information Systems Abstracts Professional</collection><jtitle>IEEE transactions on emerging topics in computing</jtitle></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Liu, Peng</au><au>You, Zhiqiang</au><au>Wu, Jigang</au><au>Elimu, Michael</au><au>Wang, Weizheng</au><au>Cai, Shuo</au><au>Han, Yinhe</au><format>journal</format><genre>article</genre><ristype>JOUR</ristype><atitle>Defect Analysis and Parallel Testing for 3D Hybrid CMOS-Memristor Memory</atitle><jtitle>IEEE transactions on emerging topics in computing</jtitle><stitle>TETC</stitle><date>2021-04-01</date><risdate>2021</risdate><volume>9</volume><issue>2</issue><spage>745</spage><epage>758</epage><pages>745-758</pages><issn>2168-6750</issn><eissn>2168-6750</eissn><coden>ITETBT</coden><abstract><![CDATA[CMOS Molecular (CMOL) architecture, which can alleviate the sneak path problem of one memristor (1R) crossbars and limit its power consumption, can be used in a large-scale memory system. In this article, we analyze the electrical defects in a CMOL circuit including open and bridge. A parallel March-like test algorithm is presented for the CMOL architecture, which covers the faults caused by the open and bridge defects and parametric variations during its fabrication. Analysis results show that the test time of the proposed test algorithm is reduced significantly compared with the enhanced methods of March-MOM and March C* for CMOL architectures. The write time is reduced approximately <inline-formula><tex-math notation="LaTeX">5n/4\times</tex-math> <mml:math><mml:mrow><mml:mn>5</mml:mn><mml:mi>n</mml:mi><mml:mo>/</mml:mo><mml:mn>4</mml:mn><mml:mo>×</mml:mo></mml:mrow></mml:math><inline-graphic xlink:href="liu-ieq1-2982830.gif"/> </inline-formula> and <inline-formula><tex-math notation="LaTeX">n\times</tex-math> <mml:math><mml:mrow><mml:mi>n</mml:mi><mml:mo>×</mml:mo></mml:mrow></mml:math><inline-graphic xlink:href="liu-ieq2-2982830.gif"/> </inline-formula>, respectively, where <inline-formula><tex-math notation="LaTeX">n</tex-math> <mml:math><mml:mi>n</mml:mi></mml:math><inline-graphic xlink:href="liu-ieq3-2982830.gif"/> </inline-formula> is the number of memristors attached to a nanowire segment. The read time is also reduced drastically. Finally, a design for testability (DFT) architecture is proposed to adapt the parallel March-like test algorithm. In compare with the short write time testing scheme, the proposed DFT can achieve 35.4 percent of reduction in area overhead, with 14.52 percent more power overhead kept the same delay in a CMOL circuit with 64 memory cells.]]></abstract><cop>New York</cop><pub>IEEE</pub><doi>10.1109/TETC.2020.2982830</doi><tpages>14</tpages><orcidid>https://orcid.org/0000-0003-4375-3187</orcidid><orcidid>https://orcid.org/0000-0002-2329-502X</orcidid><orcidid>https://orcid.org/0000-0002-6470-9794</orcidid><orcidid>https://orcid.org/0000-0001-9924-0685</orcidid><orcidid>https://orcid.org/0000-0003-0904-6681</orcidid></addata></record> |
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| subjects | Algorithms Circuit faults Circuits CMOL CMOS Computer architecture Computer memory Defects Discrete Fourier transforms memristor Memristors Nanowires Non-volatile memory Power consumption Random access memory Resistance RRAM Testability Testing Testing time |
| title | Defect Analysis and Parallel Testing for 3D Hybrid CMOS-Memristor Memory |
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