A 130 nm generation logic technology featuring 70 nm transistors, dual Vt transistors and 6 layers of Cu interconnects

A leading edge 130 nm generation logic technology with 6 layers of dual damascene Cu interconnects is reported. Dual Vt transistors are employed with 1.5 nm thick gate oxide and operating at 1.3 V. High Vt transistors have drive currents of 1.03 mA//spl mu/m and 0.5 mA//spl mu/m for NMOS and PMOS re...

Ausführliche Beschreibung

Bibliographische Detailangaben

Hauptverfasser:	Tyagi, S., Alavi, M., Bigwood, R., Bramblett, T., Brandenburg, J., Chen, W., Crew, B., Hussein, M., Jacob, P., Kenyon, C., Lo, C., McIntyre, B., Ma, Z., Moon, P., Nguyen, P., Rumaner, L., Schweinfurth, R., Sivakumar, S., Stettler, M., Thompson, S., Tufts, B., Xu, J., Yang, S., Bohr, M.
Format:	Tagungsbericht
Sprache:	eng ; jpn
Schlagworte:	Boron CMOS technology Integrated circuit interconnections Isolation technology Logic MOS devices MOSFETs Random access memory Silicon Threshold voltage
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