A novel algorithm for multi-node bridge analysis of large VLSI circuits
Defects that short two or more modes are known as multinode bridges. Multinode bridge analysis can be used to extract a list of either only two-node bridges or multi-node bridges. We discuss why multi-node bridge analysis is also required even if only two-node bridges are targeted. We propose a nove...
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| creator | Zachariah, S.T. Chakravarty, S. |
| description | Defects that short two or more modes are known as multinode bridges. Multinode bridge analysis can be used to extract a list of either only two-node bridges or multi-node bridges. We discuss why multi-node bridge analysis is also required even if only two-node bridges are targeted. We propose a novel, scalable and accurate algorithm for multinode bridge analysis of large layouts. CARAFE can perform multi-node analysis only on small layouts. Comparison results show that for small layouts our algorithm is considerably faster than CARAFE. For larger layouts experimental results are provided to illustrate the performance and capacity of our algorithm. |
| doi_str_mv | 10.1109/ICVD.2001.902681 |
| format | Conference Proceeding |
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Multinode bridge analysis can be used to extract a list of either only two-node bridges or multi-node bridges. We discuss why multi-node bridge analysis is also required even if only two-node bridges are targeted. We propose a novel, scalable and accurate algorithm for multinode bridge analysis of large layouts. CARAFE can perform multi-node analysis only on small layouts. Comparison results show that for small layouts our algorithm is considerably faster than CARAFE. For larger layouts experimental results are provided to illustrate the performance and capacity of our algorithm.</description><subject>Algorithm design and analysis</subject><subject>Bridge circuits</subject><subject>Circuit analysis</subject><subject>Circuit faults</subject><subject>Circuit testing</subject><subject>Computer aided manufacturing</subject><subject>Geometry</subject><subject>Performance analysis</subject><subject>Very large scale integration</subject><subject>Yield estimation</subject><issn>1063-9667</issn><issn>2380-6923</issn><isbn>9780769508313</isbn><isbn>0769508316</isbn><fulltext>true</fulltext><rsrctype>conference_proceeding</rsrctype><creationdate>2001</creationdate><recordtype>conference_proceeding</recordtype><sourceid>6IE</sourceid><sourceid>RIE</sourceid><recordid>eNotkEtLw0AURgcfYKzdi6v5A6n3zk3msSxRayDgQu22TDKTOpKHTFKh_95CXX1wFgfOx9g9wgoRzGNZbJ9WAgBXBoTUeMESQRpSaQRdsqVRGpQ0OWhCumIJgqTUSKlu2O00fQOAzkElbLPmw_jrO267_RjD_NXzdoy8P3RzSIfReV7H4Pae28F2xylMfGx5Z-OJbKv3kjchNocwT3fsurXd5Jf_u2CfL88fxWtavW3KYl2lASGbU026dY4woxzJN86ja1RupBMgrfIKhHAqs0A5ObRooW5cgwpPUS3puqYFezh7g_d-9xNDb-Nxd76A_gBqdkzN</recordid><startdate>2001</startdate><enddate>2001</enddate><creator>Zachariah, S.T.</creator><creator>Chakravarty, S.</creator><general>IEEE</general><scope>6IE</scope><scope>6IL</scope><scope>CBEJK</scope><scope>RIE</scope><scope>RIL</scope></search><sort><creationdate>2001</creationdate><title>A novel algorithm for multi-node bridge analysis of large VLSI circuits</title><author>Zachariah, S.T. ; Chakravarty, S.</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-i104t-838fdd3143513ecde1dc7596d206a7e7022d74a0353d1a1a0bcdc171923f38bb3</frbrgroupid><rsrctype>conference_proceedings</rsrctype><prefilter>conference_proceedings</prefilter><language>eng</language><creationdate>2001</creationdate><topic>Algorithm design and analysis</topic><topic>Bridge circuits</topic><topic>Circuit analysis</topic><topic>Circuit faults</topic><topic>Circuit testing</topic><topic>Computer aided manufacturing</topic><topic>Geometry</topic><topic>Performance analysis</topic><topic>Very large scale integration</topic><topic>Yield estimation</topic><toplevel>online_resources</toplevel><creatorcontrib>Zachariah, S.T.</creatorcontrib><creatorcontrib>Chakravarty, S.</creatorcontrib><collection>IEEE Electronic Library (IEL) Conference Proceedings</collection><collection>IEEE Proceedings Order Plan All Online (POP All Online) 1998-present by volume</collection><collection>IEEE Xplore All Conference Proceedings</collection><collection>IEEE Electronic Library (IEL)</collection><collection>IEEE Proceedings Order Plans (POP All) 1998-Present</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Zachariah, S.T.</au><au>Chakravarty, S.</au><format>book</format><genre>proceeding</genre><ristype>CONF</ristype><atitle>A novel algorithm for multi-node bridge analysis of large VLSI circuits</atitle><btitle>VLSI Design 2001. Fourteenth International Conference on VLSI Design</btitle><stitle>ICVD</stitle><date>2001</date><risdate>2001</risdate><spage>333</spage><epage>338</epage><pages>333-338</pages><issn>1063-9667</issn><eissn>2380-6923</eissn><isbn>9780769508313</isbn><isbn>0769508316</isbn><abstract>Defects that short two or more modes are known as multinode bridges. Multinode bridge analysis can be used to extract a list of either only two-node bridges or multi-node bridges. We discuss why multi-node bridge analysis is also required even if only two-node bridges are targeted. We propose a novel, scalable and accurate algorithm for multinode bridge analysis of large layouts. CARAFE can perform multi-node analysis only on small layouts. Comparison results show that for small layouts our algorithm is considerably faster than CARAFE. For larger layouts experimental results are provided to illustrate the performance and capacity of our algorithm.</abstract><pub>IEEE</pub><doi>10.1109/ICVD.2001.902681</doi><tpages>6</tpages></addata></record> |
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| identifier | ISSN: 1063-9667 |
| ispartof | VLSI Design 2001. Fourteenth International Conference on VLSI Design, 2001, p.333-338 |
| issn | 1063-9667 2380-6923 |
| language | eng |
| recordid | cdi_ieee_primary_902681 |
| source | IEEE Electronic Library (IEL) Conference Proceedings |
| subjects | Algorithm design and analysis Bridge circuits Circuit analysis Circuit faults Circuit testing Computer aided manufacturing Geometry Performance analysis Very large scale integration Yield estimation |
| title | A novel algorithm for multi-node bridge analysis of large VLSI circuits |
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