Wafer probe process verification tools
We present some tools we have developed that ensure the good quality of the wafer probing, or wafer test, process. Most of the problems at Wafer Probe appear in the same way and by detecting their pattern, even not knowing the exact source of the problem, we can prevent the product and its yield fro...
Gespeichert in:
| Hauptverfasser: | , , , |
|---|---|
| Format: | Tagungsbericht |
| Sprache: | eng |
| Schlagworte: | |
| Online-Zugang: | Volltext bestellen |
| Tags: |
Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
|
| container_end_page | 212 |
|---|---|
| container_issue | |
| container_start_page | 207 |
| container_title | |
| container_volume | |
| creator | Rodriguez, E. Cano, C. Sanchez-Vicente, J. Moreno, J. |
| description | We present some tools we have developed that ensure the good quality of the wafer probing, or wafer test, process. Most of the problems at Wafer Probe appear in the same way and by detecting their pattern, even not knowing the exact source of the problem, we can prevent the product and its yield from being affected. The most common patterns of failures are: A certain category failing consecutively, a certain test failing above statistical limits expected, based on the historical results of that product, same wafers yielding different in two different testers, and results in a lot going worse wafer by wafer. For addressing these issues, we have generated a set of programs that are run at the end of every wafer tested, in real time, and that generate alarms and tell actions to the operator when the above problems are detected. |
| doi_str_mv | 10.1109/ASMC.2000.902589 |
| format | Conference Proceeding |
| fullrecord | <record><control><sourceid>ieee_6IE</sourceid><recordid>TN_cdi_ieee_primary_902589</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><ieee_id>902589</ieee_id><sourcerecordid>902589</sourcerecordid><originalsourceid>FETCH-LOGICAL-i242t-b8e4eb9bd6376b4a4a9292772e0c7a80b12116573e4a015439f863623cf81d313</originalsourceid><addsrcrecordid>eNotT01Lw0AUXPwAQ81dPOXkLfG9t9_HErQKlR6qeCy76QusVFOyQfDfG6kwzDCHGWaEuEFoEMHfL7cvbUMA0Hgg7fyZKEhaUxvj7bkovXUwQ2pPqC9EgbOrnVXySpQ5f8w5UFpZZwtx9x56HqvjOET-445zrr55TH3qwpSGr2oahkO-Fpd9OGQu_3Uh3h4fXtuner1ZPbfLdZ1I0VRHx4qjj3szr4kqqODJk7XE0NngICIhGm0lqwColfS9M9KQ7HqHe4lyIW5PvYmZd8cxfYbxZ3c6KX8BkMVBSg</addsrcrecordid><sourcetype>Publisher</sourcetype><iscdi>true</iscdi><recordtype>conference_proceeding</recordtype></control><display><type>conference_proceeding</type><title>Wafer probe process verification tools</title><source>IEEE Electronic Library (IEL) Conference Proceedings</source><creator>Rodriguez, E. ; Cano, C. ; Sanchez-Vicente, J. ; Moreno, J.</creator><creatorcontrib>Rodriguez, E. ; Cano, C. ; Sanchez-Vicente, J. ; Moreno, J.</creatorcontrib><description>We present some tools we have developed that ensure the good quality of the wafer probing, or wafer test, process. Most of the problems at Wafer Probe appear in the same way and by detecting their pattern, even not knowing the exact source of the problem, we can prevent the product and its yield from being affected. The most common patterns of failures are: A certain category failing consecutively, a certain test failing above statistical limits expected, based on the historical results of that product, same wafers yielding different in two different testers, and results in a lot going worse wafer by wafer. For addressing these issues, we have generated a set of programs that are run at the end of every wafer tested, in real time, and that generate alarms and tell actions to the operator when the above problems are detected.</description><identifier>ISSN: 1078-8743</identifier><identifier>ISBN: 9780780359215</identifier><identifier>ISBN: 0780359216</identifier><identifier>EISSN: 2376-6697</identifier><identifier>DOI: 10.1109/ASMC.2000.902589</identifier><language>eng</language><publisher>IEEE</publisher><subject>Aluminum ; Clamps ; Instruments ; Needles ; Pins ; Probes ; Relays ; Semiconductor device manufacture ; Semiconductor device testing ; Voltage</subject><ispartof>2000 IEEE/SEMI Advanced Semiconductor Manufacturing Conference and Workshop. ASMC 2000 (Cat. No.00CH37072), 2000, p.207-212</ispartof><lds50>peer_reviewed</lds50><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://ieeexplore.ieee.org/document/902589$$EHTML$$P50$$Gieee$$H</linktohtml><link.rule.ids>310,311,781,785,790,791,2059,4051,4052,27930,54925</link.rule.ids><linktorsrc>$$Uhttps://ieeexplore.ieee.org/document/902589$$EView_record_in_IEEE$$FView_record_in_$$GIEEE</linktorsrc></links><search><creatorcontrib>Rodriguez, E.</creatorcontrib><creatorcontrib>Cano, C.</creatorcontrib><creatorcontrib>Sanchez-Vicente, J.</creatorcontrib><creatorcontrib>Moreno, J.</creatorcontrib><title>Wafer probe process verification tools</title><title>2000 IEEE/SEMI Advanced Semiconductor Manufacturing Conference and Workshop. ASMC 2000 (Cat. No.00CH37072)</title><addtitle>ASMC</addtitle><description>We present some tools we have developed that ensure the good quality of the wafer probing, or wafer test, process. Most of the problems at Wafer Probe appear in the same way and by detecting their pattern, even not knowing the exact source of the problem, we can prevent the product and its yield from being affected. The most common patterns of failures are: A certain category failing consecutively, a certain test failing above statistical limits expected, based on the historical results of that product, same wafers yielding different in two different testers, and results in a lot going worse wafer by wafer. For addressing these issues, we have generated a set of programs that are run at the end of every wafer tested, in real time, and that generate alarms and tell actions to the operator when the above problems are detected.</description><subject>Aluminum</subject><subject>Clamps</subject><subject>Instruments</subject><subject>Needles</subject><subject>Pins</subject><subject>Probes</subject><subject>Relays</subject><subject>Semiconductor device manufacture</subject><subject>Semiconductor device testing</subject><subject>Voltage</subject><issn>1078-8743</issn><issn>2376-6697</issn><isbn>9780780359215</isbn><isbn>0780359216</isbn><fulltext>true</fulltext><rsrctype>conference_proceeding</rsrctype><creationdate>2000</creationdate><recordtype>conference_proceeding</recordtype><sourceid>6IE</sourceid><sourceid>RIE</sourceid><recordid>eNotT01Lw0AUXPwAQ81dPOXkLfG9t9_HErQKlR6qeCy76QusVFOyQfDfG6kwzDCHGWaEuEFoEMHfL7cvbUMA0Hgg7fyZKEhaUxvj7bkovXUwQ2pPqC9EgbOrnVXySpQ5f8w5UFpZZwtx9x56HqvjOET-445zrr55TH3qwpSGr2oahkO-Fpd9OGQu_3Uh3h4fXtuner1ZPbfLdZ1I0VRHx4qjj3szr4kqqODJk7XE0NngICIhGm0lqwColfS9M9KQ7HqHe4lyIW5PvYmZd8cxfYbxZ3c6KX8BkMVBSg</recordid><startdate>2000</startdate><enddate>2000</enddate><creator>Rodriguez, E.</creator><creator>Cano, C.</creator><creator>Sanchez-Vicente, J.</creator><creator>Moreno, J.</creator><general>IEEE</general><scope>6IE</scope><scope>6IH</scope><scope>CBEJK</scope><scope>RIE</scope><scope>RIO</scope></search><sort><creationdate>2000</creationdate><title>Wafer probe process verification tools</title><author>Rodriguez, E. ; Cano, C. ; Sanchez-Vicente, J. ; Moreno, J.</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-i242t-b8e4eb9bd6376b4a4a9292772e0c7a80b12116573e4a015439f863623cf81d313</frbrgroupid><rsrctype>conference_proceedings</rsrctype><prefilter>conference_proceedings</prefilter><language>eng</language><creationdate>2000</creationdate><topic>Aluminum</topic><topic>Clamps</topic><topic>Instruments</topic><topic>Needles</topic><topic>Pins</topic><topic>Probes</topic><topic>Relays</topic><topic>Semiconductor device manufacture</topic><topic>Semiconductor device testing</topic><topic>Voltage</topic><toplevel>peer_reviewed</toplevel><toplevel>online_resources</toplevel><creatorcontrib>Rodriguez, E.</creatorcontrib><creatorcontrib>Cano, C.</creatorcontrib><creatorcontrib>Sanchez-Vicente, J.</creatorcontrib><creatorcontrib>Moreno, J.</creatorcontrib><collection>IEEE Electronic Library (IEL) Conference Proceedings</collection><collection>IEEE Proceedings Order Plan (POP) 1998-present by volume</collection><collection>IEEE Xplore All Conference Proceedings</collection><collection>IEEE Electronic Library (IEL)</collection><collection>IEEE Proceedings Order Plans (POP) 1998-present</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Rodriguez, E.</au><au>Cano, C.</au><au>Sanchez-Vicente, J.</au><au>Moreno, J.</au><format>book</format><genre>proceeding</genre><ristype>CONF</ristype><atitle>Wafer probe process verification tools</atitle><btitle>2000 IEEE/SEMI Advanced Semiconductor Manufacturing Conference and Workshop. ASMC 2000 (Cat. No.00CH37072)</btitle><stitle>ASMC</stitle><date>2000</date><risdate>2000</risdate><spage>207</spage><epage>212</epage><pages>207-212</pages><issn>1078-8743</issn><eissn>2376-6697</eissn><isbn>9780780359215</isbn><isbn>0780359216</isbn><abstract>We present some tools we have developed that ensure the good quality of the wafer probing, or wafer test, process. Most of the problems at Wafer Probe appear in the same way and by detecting their pattern, even not knowing the exact source of the problem, we can prevent the product and its yield from being affected. The most common patterns of failures are: A certain category failing consecutively, a certain test failing above statistical limits expected, based on the historical results of that product, same wafers yielding different in two different testers, and results in a lot going worse wafer by wafer. For addressing these issues, we have generated a set of programs that are run at the end of every wafer tested, in real time, and that generate alarms and tell actions to the operator when the above problems are detected.</abstract><pub>IEEE</pub><doi>10.1109/ASMC.2000.902589</doi><tpages>6</tpages></addata></record> |
| fulltext | fulltext_linktorsrc |
| identifier | ISSN: 1078-8743 |
| ispartof | 2000 IEEE/SEMI Advanced Semiconductor Manufacturing Conference and Workshop. ASMC 2000 (Cat. No.00CH37072), 2000, p.207-212 |
| issn | 1078-8743 2376-6697 |
| language | eng |
| recordid | cdi_ieee_primary_902589 |
| source | IEEE Electronic Library (IEL) Conference Proceedings |
| subjects | Aluminum Clamps Instruments Needles Pins Probes Relays Semiconductor device manufacture Semiconductor device testing Voltage |
| title | Wafer probe process verification tools |
| url | https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2024-12-16T13%3A11%3A54IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-ieee_6IE&rft_val_fmt=info:ofi/fmt:kev:mtx:book&rft.genre=proceeding&rft.atitle=Wafer%20probe%20process%20verification%20tools&rft.btitle=2000%20IEEE/SEMI%20Advanced%20Semiconductor%20Manufacturing%20Conference%20and%20Workshop.%20ASMC%202000%20(Cat.%20No.00CH37072)&rft.au=Rodriguez,%20E.&rft.date=2000&rft.spage=207&rft.epage=212&rft.pages=207-212&rft.issn=1078-8743&rft.eissn=2376-6697&rft.isbn=9780780359215&rft.isbn_list=0780359216&rft_id=info:doi/10.1109/ASMC.2000.902589&rft_dat=%3Cieee_6IE%3E902589%3C/ieee_6IE%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rft_ieee_id=902589&rfr_iscdi=true |