Efficient random vector verification method for an embedded 32-bit RISC core

Processors require both intensive and extensive functional verification in their design phase to satisfy their general purposability. The proposed random vector verification method for CalmRISC/sup TM/-32 core meets this goal by contributing complementary assistance for conventional verification met...

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Bibliographische Detailangaben

Hauptverfasser:	Chang-Ho Lee, Hoon-Mo Yang, Sung-Ho Kwak, Moon-Key Lee, Sanghyun Park, Sangyeun Cho, Sangwoo Kim, Yongchun Kim, Seh-Woong Jeong, Bong-Young Chung, Hyung-Lae Roh
Format:	Tagungsbericht
Sprache:	eng
Schlagworte:	Clocks Delay Design engineering Embedded computing Hardware design languages Large scale integration Pipelines Reduced instruction set computing Registers Timing
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