Efficient random vector verification method for an embedded 32-bit RISC core
Processors require both intensive and extensive functional verification in their design phase to satisfy their general purposability. The proposed random vector verification method for CalmRISC/sup TM/-32 core meets this goal by contributing complementary assistance for conventional verification met...
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creator | Chang-Ho Lee Hoon-Mo Yang Sung-Ho Kwak Moon-Key Lee Sanghyun Park Sangyeun Cho Sangwoo Kim Yongchun Kim Seh-Woong Jeong Bong-Young Chung Hyung-Lae Roh |
description | Processors require both intensive and extensive functional verification in their design phase to satisfy their general purposability. The proposed random vector verification method for CalmRISC/sup TM/-32 core meets this goal by contributing complementary assistance for conventional verification methods. It adopts a cycle-accurate instruction level simulator as a reference model, runs simulation in both the reference and the target HDL and reports errors if any difference is found between them. These processes are automatically performed in the unified environment. The instruction level simulator, the core part in the verification environment is able to simulate almost every aspect of RISC processors from functional behavior of each opcode to timing details in the pipeline flow in fast speed. Its design style from microprogramming scheme also makes its structure modular and flexible. |
doi_str_mv | 10.1109/APASIC.2000.896965 |
format | Conference Proceeding |
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identifier | ISBN: 0780364708 |
ispartof | Proceedings of Second IEEE Asia Pacific Conference on ASICs. AP-ASIC 2000 (Cat. No.00EX434), 2000, p.291-294 |
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language | eng |
recordid | cdi_ieee_primary_896965 |
source | IEEE Electronic Library (IEL) Conference Proceedings |
subjects | Clocks Delay Design engineering Embedded computing Hardware design languages Large scale integration Pipelines Reduced instruction set computing Registers Timing |
title | Efficient random vector verification method for an embedded 32-bit RISC core |
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