Cyclic greedy generation method for limited number of IDDQ tests
This paper proposes a generation method (called Cyclic Greedy generation method) of IDDQ test sets for maximizing the number of detected faults under the constraint that the number of test patterns is limited. First this method greedily generates the given limited number of test patterns, then it gr...
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| creator | Shinogi, T. Ushio, M. Hayashi, T. |
| description | This paper proposes a generation method (called Cyclic Greedy generation method) of IDDQ test sets for maximizing the number of detected faults under the constraint that the number of test patterns is limited. First this method greedily generates the given limited number of test patterns, then it greedily re-generates each pattern sequentially all over again and again in a cyclic manner. Each test pattern is generated by the iterative improvement method of random patterns. The experimental results show that the number of undetected faults remained by the Cyclic Greedy generation method is 13% less than by the pure greedy generation method in average for the large ISCAS85&89 circuits. |
| doi_str_mv | 10.1109/ATS.2000.893650 |
| format | Conference Proceeding |
| fullrecord | <record><control><sourceid>proquest_6IE</sourceid><recordid>TN_cdi_ieee_primary_893650</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><ieee_id>893650</ieee_id><sourcerecordid>27247961</sourcerecordid><originalsourceid>FETCH-LOGICAL-i203t-61d9cf0f5c28e11f54ff1e97abf58a8cb28e80e06a40124e2ff15192b4858a293</originalsourceid><addsrcrecordid>eNotUDlrwzAYFT2gSdq50ElTN6efJMuStoakRyBQStPZyPanVMVHKjmD_30M7vTgnfAIuWewZAzM02r_teQAsNRGZBIuyIwLpRIpdHZJ5qAyI0Frxa7IjIFmiVJC3pB5jL9jSIARM_K8Hsral_QQEKuBHrDFYHvftbTB_qerqOsCrX3je6xoe2oKDLRzdLvZfNIeYx9vybWzdcS7f1yQ79eX_fo92X28bderXeI5iD7JWGVKB06WXCNjTqbOMTTKFk5qq8tipDUgZDYFxlPkoyyZ4UWqR50bsSCPU-8xdH-ncTlvfCyxrm2L3SnmXPFUmYyNxofJ6BExPwbf2DDk00PiDEioVuQ</addsrcrecordid><sourcetype>Aggregation Database</sourcetype><iscdi>true</iscdi><recordtype>conference_proceeding</recordtype><pqid>27247961</pqid></control><display><type>conference_proceeding</type><title>Cyclic greedy generation method for limited number of IDDQ tests</title><source>IEEE Electronic Library (IEL) Conference Proceedings</source><creator>Shinogi, T. ; Ushio, M. ; Hayashi, T.</creator><creatorcontrib>Shinogi, T. ; Ushio, M. ; Hayashi, T.</creatorcontrib><description>This paper proposes a generation method (called Cyclic Greedy generation method) of IDDQ test sets for maximizing the number of detected faults under the constraint that the number of test patterns is limited. First this method greedily generates the given limited number of test patterns, then it greedily re-generates each pattern sequentially all over again and again in a cyclic manner. Each test pattern is generated by the iterative improvement method of random patterns. The experimental results show that the number of undetected faults remained by the Cyclic Greedy generation method is 13% less than by the pure greedy generation method in average for the large ISCAS85&89 circuits.</description><identifier>ISSN: 1081-7735</identifier><identifier>ISBN: 0769508871</identifier><identifier>ISBN: 9780769508870</identifier><identifier>EISSN: 2377-5386</identifier><identifier>DOI: 10.1109/ATS.2000.893650</identifier><language>eng</language><publisher>IEEE</publisher><subject>Circuit faults ; Circuit testing ; CMOS logic circuits ; Electrical fault detection ; Electronic equipment testing ; Fault detection ; Logic testing ; Random number generation ; Sequential analysis ; Test pattern generators</subject><ispartof>Proceedings - Asian Test Symposium, 2000, p.362-366</ispartof><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://ieeexplore.ieee.org/document/893650$$EHTML$$P50$$Gieee$$H</linktohtml><link.rule.ids>309,310,776,780,785,786,2051,4035,4036,27904,54899</link.rule.ids><linktorsrc>$$Uhttps://ieeexplore.ieee.org/document/893650$$EView_record_in_IEEE$$FView_record_in_$$GIEEE</linktorsrc></links><search><creatorcontrib>Shinogi, T.</creatorcontrib><creatorcontrib>Ushio, M.</creatorcontrib><creatorcontrib>Hayashi, T.</creatorcontrib><title>Cyclic greedy generation method for limited number of IDDQ tests</title><title>Proceedings - Asian Test Symposium</title><addtitle>ATS</addtitle><description>This paper proposes a generation method (called Cyclic Greedy generation method) of IDDQ test sets for maximizing the number of detected faults under the constraint that the number of test patterns is limited. First this method greedily generates the given limited number of test patterns, then it greedily re-generates each pattern sequentially all over again and again in a cyclic manner. Each test pattern is generated by the iterative improvement method of random patterns. The experimental results show that the number of undetected faults remained by the Cyclic Greedy generation method is 13% less than by the pure greedy generation method in average for the large ISCAS85&89 circuits.</description><subject>Circuit faults</subject><subject>Circuit testing</subject><subject>CMOS logic circuits</subject><subject>Electrical fault detection</subject><subject>Electronic equipment testing</subject><subject>Fault detection</subject><subject>Logic testing</subject><subject>Random number generation</subject><subject>Sequential analysis</subject><subject>Test pattern generators</subject><issn>1081-7735</issn><issn>2377-5386</issn><isbn>0769508871</isbn><isbn>9780769508870</isbn><fulltext>true</fulltext><rsrctype>conference_proceeding</rsrctype><creationdate>2000</creationdate><recordtype>conference_proceeding</recordtype><sourceid>6IE</sourceid><sourceid>RIE</sourceid><recordid>eNotUDlrwzAYFT2gSdq50ElTN6efJMuStoakRyBQStPZyPanVMVHKjmD_30M7vTgnfAIuWewZAzM02r_teQAsNRGZBIuyIwLpRIpdHZJ5qAyI0Frxa7IjIFmiVJC3pB5jL9jSIARM_K8Hsral_QQEKuBHrDFYHvftbTB_qerqOsCrX3je6xoe2oKDLRzdLvZfNIeYx9vybWzdcS7f1yQ79eX_fo92X28bderXeI5iD7JWGVKB06WXCNjTqbOMTTKFk5qq8tipDUgZDYFxlPkoyyZ4UWqR50bsSCPU-8xdH-ncTlvfCyxrm2L3SnmXPFUmYyNxofJ6BExPwbf2DDk00PiDEioVuQ</recordid><startdate>2000</startdate><enddate>2000</enddate><creator>Shinogi, T.</creator><creator>Ushio, M.</creator><creator>Hayashi, T.</creator><general>IEEE</general><scope>6IE</scope><scope>6IL</scope><scope>CBEJK</scope><scope>RIE</scope><scope>RIL</scope><scope>7SC</scope><scope>8FD</scope><scope>JQ2</scope><scope>L7M</scope><scope>L~C</scope><scope>L~D</scope></search><sort><creationdate>2000</creationdate><title>Cyclic greedy generation method for limited number of IDDQ tests</title><author>Shinogi, T. ; Ushio, M. ; Hayashi, T.</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-i203t-61d9cf0f5c28e11f54ff1e97abf58a8cb28e80e06a40124e2ff15192b4858a293</frbrgroupid><rsrctype>conference_proceedings</rsrctype><prefilter>conference_proceedings</prefilter><language>eng</language><creationdate>2000</creationdate><topic>Circuit faults</topic><topic>Circuit testing</topic><topic>CMOS logic circuits</topic><topic>Electrical fault detection</topic><topic>Electronic equipment testing</topic><topic>Fault detection</topic><topic>Logic testing</topic><topic>Random number generation</topic><topic>Sequential analysis</topic><topic>Test pattern generators</topic><toplevel>online_resources</toplevel><creatorcontrib>Shinogi, T.</creatorcontrib><creatorcontrib>Ushio, M.</creatorcontrib><creatorcontrib>Hayashi, T.</creatorcontrib><collection>IEEE Electronic Library (IEL) Conference Proceedings</collection><collection>IEEE Proceedings Order Plan All Online (POP All Online) 1998-present by volume</collection><collection>IEEE Xplore All Conference Proceedings</collection><collection>IEEE Electronic Library (IEL)</collection><collection>IEEE Proceedings Order Plans (POP All) 1998-Present</collection><collection>Computer and Information Systems Abstracts</collection><collection>Technology Research Database</collection><collection>ProQuest Computer Science Collection</collection><collection>Advanced Technologies Database with Aerospace</collection><collection>Computer and Information Systems Abstracts Academic</collection><collection>Computer and Information Systems Abstracts Professional</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Shinogi, T.</au><au>Ushio, M.</au><au>Hayashi, T.</au><format>book</format><genre>proceeding</genre><ristype>CONF</ristype><atitle>Cyclic greedy generation method for limited number of IDDQ tests</atitle><btitle>Proceedings - Asian Test Symposium</btitle><stitle>ATS</stitle><date>2000</date><risdate>2000</risdate><spage>362</spage><epage>366</epage><pages>362-366</pages><issn>1081-7735</issn><eissn>2377-5386</eissn><isbn>0769508871</isbn><isbn>9780769508870</isbn><abstract>This paper proposes a generation method (called Cyclic Greedy generation method) of IDDQ test sets for maximizing the number of detected faults under the constraint that the number of test patterns is limited. First this method greedily generates the given limited number of test patterns, then it greedily re-generates each pattern sequentially all over again and again in a cyclic manner. Each test pattern is generated by the iterative improvement method of random patterns. The experimental results show that the number of undetected faults remained by the Cyclic Greedy generation method is 13% less than by the pure greedy generation method in average for the large ISCAS85&89 circuits.</abstract><pub>IEEE</pub><doi>10.1109/ATS.2000.893650</doi><tpages>5</tpages></addata></record> |
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| language | eng |
| recordid | cdi_ieee_primary_893650 |
| source | IEEE Electronic Library (IEL) Conference Proceedings |
| subjects | Circuit faults Circuit testing CMOS logic circuits Electrical fault detection Electronic equipment testing Fault detection Logic testing Random number generation Sequential analysis Test pattern generators |
| title | Cyclic greedy generation method for limited number of IDDQ tests |
| url | https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-01-21T17%3A33%3A17IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-proquest_6IE&rft_val_fmt=info:ofi/fmt:kev:mtx:book&rft.genre=proceeding&rft.atitle=Cyclic%20greedy%20generation%20method%20for%20limited%20number%20of%20IDDQ%20tests&rft.btitle=Proceedings%20-%20Asian%20Test%20Symposium&rft.au=Shinogi,%20T.&rft.date=2000&rft.spage=362&rft.epage=366&rft.pages=362-366&rft.issn=1081-7735&rft.eissn=2377-5386&rft.isbn=0769508871&rft.isbn_list=9780769508870&rft_id=info:doi/10.1109/ATS.2000.893650&rft_dat=%3Cproquest_6IE%3E27247961%3C/proquest_6IE%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_pqid=27247961&rft_id=info:pmid/&rft_ieee_id=893650&rfr_iscdi=true |