A Power-Efficient Digital Technique for Gain and Offset Correction in Slope ADCs
In this brief, a power-efficient digital technique for gain and offset correction in slope analog-to-digital converters (ADCs) has been proposed. The technique is especially useful for imaging arrays with massively parallel image acquisition where simultaneous compensation of dark signal non-uniform...
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| Veröffentlicht in: | IEEE transactions on circuits and systems. II, Express briefs Express briefs, 2020-06, Vol.67 (6), p.979-983 |
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| container_title | IEEE transactions on circuits and systems. II, Express briefs |
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| creator | Klosowski, M. |
| description | In this brief, a power-efficient digital technique for gain and offset correction in slope analog-to-digital converters (ADCs) has been proposed. The technique is especially useful for imaging arrays with massively parallel image acquisition where simultaneous compensation of dark signal non-uniformity (DSNU) as well as photo-response non-uniformity (PRNU) is critical. The presented approach is based on stopping the ADC clock by a specially prepared clock-enable pulse sequence. This brief describes the properties of ADCs utilizing this clock stopping technique, including power dissipation, integral, and differential nonlinearity. The experimental validation has been performed for the ASIC implementation of the 128-pixel imager containing photo-sensors integrated with ADCs. Finally, a modification is proposed that increases the accuracy of the gain correction. Measurements confirm functionality of the proposed approach. Reduction of the PRNU (to ~0.4 LSB) has been achieved as well. |
| doi_str_mv | 10.1109/TCSII.2019.2928183 |
| format | Article |
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The technique is especially useful for imaging arrays with massively parallel image acquisition where simultaneous compensation of dark signal non-uniformity (DSNU) as well as photo-response non-uniformity (PRNU) is critical. The presented approach is based on stopping the ADC clock by a specially prepared clock-enable pulse sequence. This brief describes the properties of ADCs utilizing this clock stopping technique, including power dissipation, integral, and differential nonlinearity. The experimental validation has been performed for the ASIC implementation of the 128-pixel imager containing photo-sensors integrated with ADCs. Finally, a modification is proposed that increases the accuracy of the gain correction. Measurements confirm functionality of the proposed approach. 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Reduction of the PRNU (to ~0.4 LSB) has been achieved as well.</description><subject>Analog to digital conversion</subject><subject>Analog to digital converters</subject><subject>Analog-digital conversion</subject><subject>Clocks</subject><subject>Digital image sensor</subject><subject>digital pixel</subject><subject>Energy consumption</subject><subject>fixed pattern noise (FPN)</subject><subject>gain correction</subject><subject>Gain measurement</subject><subject>Image acquisition</subject><subject>Logic gates</subject><subject>Nonuniformity</subject><subject>offset correction</subject><subject>photo-response non-uniformity (PRNU)</subject><subject>Power demand</subject><subject>Pulse generation</subject><issn>1549-7747</issn><issn>1558-3791</issn><fulltext>true</fulltext><rsrctype>article</rsrctype><creationdate>2020</creationdate><recordtype>article</recordtype><sourceid>RIE</sourceid><recordid>eNo9kE1LAzEQhoMoWKt_QC8Bz1vzsfk6lm2thUILreeQbiaaUjc1u0X8926teJqBeZ-Z4UHonpIRpcQ8bar1fD5ihJoRM0xTzS_QgAqhC64MvTz1pSmUKtU1umnbHSHMEM4GaDXGq_QFuZiGEOsITYcn8S12bo83UL838fMIOKSMZy422DUeL0NoocNVyhnqLqYG94P1Ph0AjydVe4uugtu3cPdXh-j1ebqpXorFcjavxouiZkZ0xdYZAYYAN1IqokntpXFOQ6BbrsAbF4T3WstaOK5Lr0pdcs-2im-DD0YRPkSP572HnPof287u0jE3_UnLSqKlUELIPsXOqTqnts0Q7CHHD5e_LSX2ZM7-mrMnc_bPXA89nKEIAP-AVpKUTPIf401pLQ</recordid><startdate>20200601</startdate><enddate>20200601</enddate><creator>Klosowski, M.</creator><general>IEEE</general><general>The Institute of Electrical and Electronics Engineers, Inc. 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The technique is especially useful for imaging arrays with massively parallel image acquisition where simultaneous compensation of dark signal non-uniformity (DSNU) as well as photo-response non-uniformity (PRNU) is critical. The presented approach is based on stopping the ADC clock by a specially prepared clock-enable pulse sequence. This brief describes the properties of ADCs utilizing this clock stopping technique, including power dissipation, integral, and differential nonlinearity. The experimental validation has been performed for the ASIC implementation of the 128-pixel imager containing photo-sensors integrated with ADCs. Finally, a modification is proposed that increases the accuracy of the gain correction. Measurements confirm functionality of the proposed approach. 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| fulltext | fulltext_linktorsrc |
| identifier | ISSN: 1549-7747 |
| ispartof | IEEE transactions on circuits and systems. II, Express briefs, 2020-06, Vol.67 (6), p.979-983 |
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| language | eng |
| recordid | cdi_ieee_primary_8760426 |
| source | IEEE Electronic Library (IEL) |
| subjects | Analog to digital conversion Analog to digital converters Analog-digital conversion Clocks Digital image sensor digital pixel Energy consumption fixed pattern noise (FPN) gain correction Gain measurement Image acquisition Logic gates Nonuniformity offset correction photo-response non-uniformity (PRNU) Power demand Pulse generation |
| title | A Power-Efficient Digital Technique for Gain and Offset Correction in Slope ADCs |
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