Performance oriented partitioning for time-multiplexed FPGA's
Time-multiplexing is a promising method to reduce the cost of FPGA based systems. It means execution of logic in consecutive steps with reconfiguration taking place between these steps. The use of time-multiplexing makes it possible to reduce the size of FPGAs but requires a new step in the design f...
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| creator | Andersson, P. Kuchcinski, K. |
| description | Time-multiplexing is a promising method to reduce the cost of FPGA based systems. It means execution of logic in consecutive steps with reconfiguration taking place between these steps. The use of time-multiplexing makes it possible to reduce the size of FPGAs but requires a new step in the design flow. The circuit has to be divided into sequential steps, partitions. In this paper we present an algorithm which partitions sequential circuits for time-multiplexing. The algorithm is based on list scheduling. Our experiments show that the algorithm is fast. It is able to partition a design with 4000 nodes in less than 4 seconds. The generated partitions have small size overhead, up to 3.2%, while no time overhead is allowed, besides the necessary reconfiguration time. |
| doi_str_mv | 10.1109/EURMIC.2000.874616 |
| format | Conference Proceeding |
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The generated partitions have small size overhead, up to 3.2%, while no time overhead is allowed, besides the necessary reconfiguration time.</description><subject>Cost function</subject><subject>Delay</subject><subject>Field programmable gate arrays</subject><subject>Job shop scheduling</subject><subject>Partitioning algorithms</subject><subject>Reconfigurable logic</subject><subject>Scheduling algorithm</subject><subject>Sequential circuits</subject><subject>Time to market</subject><subject>Virtual prototyping</subject><issn>1089-6503</issn><issn>2376-9505</issn><isbn>0769507808</isbn><isbn>9780769507804</isbn><fulltext>true</fulltext><rsrctype>conference_proceeding</rsrctype><creationdate>2000</creationdate><recordtype>conference_proceeding</recordtype><sourceid>6IE</sourceid><sourceid>RIE</sourceid><recordid>eNotj0tLAzEcxIMPcK39Aj3tzVPWf97JwUNZ2lqoWKSeS3aTSGRfZFfQb-9CPc3A_GZgEFoRKAgB87T5eH_dlwUFgEIrLom8QhllSmIjQFyje1BydkqDvkEZAW2wFMDu0HIcv-YSCKEZQIaejz6FPrW2q33ep-i7ybt8sGmKU-y72H3mc5xPsfW4_W6mODT-Zya2x936cXxAt8E2o1_-6wKdtptT-YIPb7t9uT7gSBSfMGW08swBASJkbY3jmhtVEW4DkaxmRLNAnaEyeEd5bStJK0UoD5IKcIYt0OoyG7335yHF1qbf8-U3-wO3ZUmv</recordid><startdate>2000</startdate><enddate>2000</enddate><creator>Andersson, P.</creator><creator>Kuchcinski, K.</creator><general>IEEE</general><scope>6IE</scope><scope>6IL</scope><scope>CBEJK</scope><scope>RIE</scope><scope>RIL</scope></search><sort><creationdate>2000</creationdate><title>Performance oriented partitioning for time-multiplexed FPGA's</title><author>Andersson, P. ; Kuchcinski, K.</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-i174t-232be3d010156ca9d48497b14af163c3183f2d926fed24cab62b7124f6250d93</frbrgroupid><rsrctype>conference_proceedings</rsrctype><prefilter>conference_proceedings</prefilter><language>eng</language><creationdate>2000</creationdate><topic>Cost function</topic><topic>Delay</topic><topic>Field programmable gate arrays</topic><topic>Job shop scheduling</topic><topic>Partitioning algorithms</topic><topic>Reconfigurable logic</topic><topic>Scheduling algorithm</topic><topic>Sequential circuits</topic><topic>Time to market</topic><topic>Virtual prototyping</topic><toplevel>online_resources</toplevel><creatorcontrib>Andersson, P.</creatorcontrib><creatorcontrib>Kuchcinski, K.</creatorcontrib><collection>IEEE Electronic Library (IEL) Conference Proceedings</collection><collection>IEEE Proceedings Order Plan All Online (POP All Online) 1998-present by volume</collection><collection>IEEE Xplore All Conference Proceedings</collection><collection>IEEE Electronic Library (IEL)</collection><collection>IEEE Proceedings Order Plans (POP All) 1998-Present</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Andersson, P.</au><au>Kuchcinski, K.</au><format>book</format><genre>proceeding</genre><ristype>CONF</ristype><atitle>Performance oriented partitioning for time-multiplexed FPGA's</atitle><btitle>Proceedings of the 26th Euromicro Conference. EUROMICRO 2000. Informatics: Inventing the Future</btitle><stitle>EURMIC</stitle><date>2000</date><risdate>2000</risdate><volume>1</volume><spage>60</spage><epage>66 vol.1</epage><pages>60-66 vol.1</pages><issn>1089-6503</issn><eissn>2376-9505</eissn><isbn>0769507808</isbn><isbn>9780769507804</isbn><abstract>Time-multiplexing is a promising method to reduce the cost of FPGA based systems. It means execution of logic in consecutive steps with reconfiguration taking place between these steps. The use of time-multiplexing makes it possible to reduce the size of FPGAs but requires a new step in the design flow. The circuit has to be divided into sequential steps, partitions. In this paper we present an algorithm which partitions sequential circuits for time-multiplexing. The algorithm is based on list scheduling. Our experiments show that the algorithm is fast. It is able to partition a design with 4000 nodes in less than 4 seconds. The generated partitions have small size overhead, up to 3.2%, while no time overhead is allowed, besides the necessary reconfiguration time.</abstract><pub>IEEE</pub><doi>10.1109/EURMIC.2000.874616</doi></addata></record> |
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| ispartof | Proceedings of the 26th Euromicro Conference. EUROMICRO 2000. Informatics: Inventing the Future, 2000, Vol.1, p.60-66 vol.1 |
| issn | 1089-6503 2376-9505 |
| language | eng |
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| source | IEEE Electronic Library (IEL) Conference Proceedings |
| subjects | Cost function Delay Field programmable gate arrays Job shop scheduling Partitioning algorithms Reconfigurable logic Scheduling algorithm Sequential circuits Time to market Virtual prototyping |
| title | Performance oriented partitioning for time-multiplexed FPGA's |
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