A Linearity-Enhanced 10-Bit 160-MS/s SAR ADC With Low-Noise Comparator Technique

This paper presents a linearity-enhanced 10-bit 160-MS/s successive approximation register (SAR) analog-to-digital converter (ADC) with a high-speed and low-noise comparator. A p-well floating technique for linearity improvement of sampling switch is proposed. The total parasitic capacitance of the...

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Veröffentlicht in:	IEEE transactions on very large scale integration (VLSI) systems 2019-09, Vol.27 (9), p.1990-1997
Hauptverfasser:	Xu, Daiguo, Jiang, Hequan, Qiu, Lei, Yu, Xiaoquan, Wang, Jianan, Zhang, Zhengping, Zhu, Can, Xu, Shiliu
Format:	Artikel
Sprache:	eng
Schlagworte:	Adaptive sampling Analog to digital conversion Analog to digital converters Analog-to-digital converter (ADC) asynchronous successive approximation register (SAR) Capacitance Capacitors CMOS Digital to analog conversion Digital to analog converters Feedback loops Floating structures high-speed and low-noise comparator Junctions Linearity linearity enhanced Noise Noise levels parallel SAR logic Parasitic capacitance Parasitics (electronics) Power consumption Power supplies Substrates Switches
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